2004-2016 刊物
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刊物文章
书籍章节
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博士论文
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2016
Y. Moursy, H. Zou, R. Khalil, R. Iskander, P. Tisserand, D.‑M. Ton, G. Pasetti, M.‑M. Louërat : “Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications ”, IEEE Transactions on Power Electronics, (Institute of Electrical and Electronics Engineers) (2016)H. Zou, Y. Moursy, R. Iskander, A. Steinmair, H. Gensinger, Eh. Seebacher, J.‑P. Chaput, M.‑M. Louërat : “Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology ”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, pp. 2323-2333 (2016)H. Zou, Y. Moursy, R. Iskander, J.‑P. Chaput, M.‑M. Louërat : “An Adaptive Mesh Refinement Strategy of Substrate Modeling for Smart Power ICs ”, IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montreal, Canada, pp. 2358-2361 (2016)Y. Moursy, R. Khalil, S. Lecce, V. Poletto, R. Iskander, M.‑M. Louërat : “Mixed-Signal PI Controller in Current-Mode DC-DC Buck Converter for Automotive Applications ”, IEEE International Symposium on Circuits and Systems (ISCAS'16), Montréal, Canada, pp. 1610-1613 (2016)Y. Moursy, H. Zou, R. Iskander, P. Tisserand, D.‑M. Ton, G. Pasetti, Eh. Seebacher, A. Steinmair, Th. Gneiting, H. Alius : “Towards Automatic Diagnosis of Minority Carriers Propagation Problems in HV/HT Automotive Smart Power ICs ”, Design, Automation & Test in Europe Conference & Exhibition (DATE) 2016 Conference, Dresde, Germany (2016)
2015
A. Malak, Y. Li, R. Iskander, F. Durbin, F. Javid, M.‑M. Louërat, A. Tissot, J.‑M. Guebhard : “Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations ”, Integration, the VLSI Journal, vol. 48, pp. 198-212, (ISBN: 0167-9260) (2015)H. Zou, Y. Moursy, R. Iskander, J.‑P. Chaput, M.‑M. Louërat, C. Stefanucci, P. Buccella, M. Kayal, J.‑M. Sallese, Th. Gneiting, H. Alius, A. Steinmair, Eh. Seebacher : “A CAD integrated solution of substrate modeling for industrial IC design ”, 2015 20th International Mixed-Signal Testing Workshop (IMSTW), Paris, France (2015)Y. Moursy, R. Iskander, M.‑M. Louërat : “Automated triangular wave generator design with process corners compensation ”, IMSTW'15 - 20th International Mixed-Signal Testing Workshop, Paris, France, pp. 1-6, (IEEE) (2015)C. Stefanucci, P. Buccella, Y. Moursy, H. Zou, R. Iskander, M. Kayal, J.‑M. Sallese : “Substrate modeling to improve reliability of high voltage technologies ”, 20th International Mixed-Signal Testing Workshop (IMSTW), 2015, Paris, Paris, France (2015)H. Zou, Y. Moursy, R. Iskander, C. Stefanucci, P. Buccella, M. Kayal, J.‑M. Sallese : “Substrate noise modeling with dedicated CAD framework for smart power ICs ”, 2015 IEEE International Symposium on Circuits and Systems (ISCAS) n°1554, Lisbon, Portugal, pp. 4 (2015)Y. Li, H. Zou, Y. Moursy, R. Iskander, R. Sobot, M.‑M. Louërat : “Optimization and Co-Simulation of an Implantable Telemetry System by Linking System Models to Nonlinear Circuits ”, chapter in Computational Intelligence in Analog an Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, M. Fakhfakh, E. Cuautle, P. Siarry (Eds.), pp. 83-113, (Springer), (ISBN: 978-3-319-19872-9) (2015)R. Iskander, F. Javid, M.‑M. Louërat : “Is there a chance that computers understand analog design? ”, (2015)
2014
H. Zou, Y. Moursy, R. Iskander, M.‑M. Louërat, J.‑P. Chaput : “A novel CAD framework for substrate modeling ”, 10th Conference on Ph.D Research in Microelectronics and electronics, Grenoble, France, pp. 1-4, (IEEE) (2014)Th. Vörtler, Th. Klotz, K. Einwich, Y. Li, Zh. Wang, M.‑M. Louërat, J.‑P. Chaput, F. Pêcheux, R. Iskander, M. Barnasconi : “Enriching UVM in SystemC with AMS extensions for randomization and coverage ”, Design and Verification Conference and Exhibition (DVCON Europe), Munich, Germany (2014)R. Lucas, E. Vaumorin, Ph. Cuenot, Y. Li, Zh. Wang, M.‑M. Louërat, J.‑P. Chaput, F. Pêcheux, R. Iskander, M. Barnasconi, Th. Vörtler, K. Einwich : “Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS extensions ”, Design and Verification Conference and Exhibition (DVCON Europe), Munich, Germany (2014)Y. Li, R. Iskander, M.‑M. Louërat : “Modeling, Design and Verification Platform using SystemC AMS ”, 15th International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, pp. 39-46, (IEEE) (2014)Y. Li, Zh. Wang, M.‑M. Louërat, F. Pêcheux, R. Iskander, Ph. Cuenot, M. Barnasconi, Th. Vörtler, K. Einwich : “Virtual Prototyping, Verification and Validation Framework for Automotive Using SystemC, SystemC-AMS and SystemC-UVM ”, Embedded Real Time Software and Systems (ERTS2), Toulouse, France, pp. 1-10 (2014)Y. Li, R. Iskander, F. Javid, M.‑M. Louërat : “A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS ”, chapter in Models, Methods, and Tools for Complex Chip Design, vol. 265, Lecture Notes in Electrical Engineering, J. Haase (Ed.), pp. 89-108, (Springer), (ISBN: 978-3-319-01417-3) (2014)
2013
R. Iskander, M.‑M. Louërat, A. Kaiser : “Hierarchical sizing and biasing of analog firm intellectual properties ”, INTEGRATION, the VLSI journal, vol. 46 (2), pp. 172-188, (ISBN: 0167-9260) (2013)F. Javid, R. Iskander, M.‑M. Louërat, F. Durbin : “A Structured DC Analysis Methodology for Accurate Verification of Analog Circuits ”, IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, pp. 2662-2665, (IEEE) (2013)Y. Moursy, S. Afara, P. Buccella, C. Stefanucci, R. Iskander, M. Kayal, J.‑M. Sallese, M.‑M. Louërat, J.‑P. Chaput, M. Thomas Tomasevic, S. Ben‑Dhia, A. Boyer, B. Guegan, V. Poletto, A. Roggero, T. Cavioni, E. Novarini, Eh. Seebacher, A. Steinmair, P. Tisserand, D.‑M. Ton, Th. Bousquet, Th. Gneiting : “AUTOMICS: A novel approach for substrate modeling for Automotive applications ”, 18th IEEE European Test Symposium, Avignon, France (2013)F. Javid, S. Youssef, R. Iskander, M.‑M. Louërat : “A Designer-Assisted Analog Synthesis Flow ”, chapter in Analog/RF and Mixed-Signal Circuit Systematic Design, vol. 233, Lecture Notes in Electrical Engineering, M. Fakhfakh, E. Cuautle, R. Castro-Lopez (Eds.), pp. 123-148, (Springer), (ISBN: 978-3-642-36328-3) (2013)S. Youssef, J.‑P. Chaput, R. Iskander, M.‑M. Louërat : “A Designer Centric Analog Layout Flow ”, (2013)R. Iskander : “European Green Car Initiative ”, (2013)
2012
F. Javid, R. Iskander, F. Durbin, M.‑M. Louërat : “Analog Circuits Sizing Using the Fixed Point Iteration Algorithm with Transistor Compact Models ”, International Journal of Microelectronics and Computer Science, vol. 3 (1), pp. 7-14, (ISBN: 2080-8755) (2012)Y. Li, R. Iskander, F. Javid, M.‑M. Louërat : “A Unified Platform for Design and Verification of Mixed-Signal Systems Based on SystemC-AMS ”, Forum on specification & Design Languages, FDL 2012, Vienna, Austria, pp. 75-82, (ISBN: 1636-9874) (2012)F. Javid, R. Iskander, F. Durbin, M.‑M. Louërat : “Analog Circuits Sizing Using the Fixed Point Iteration Algorithm with Transistor Compact Models ”, 19th IEEE International Mixed Design of Integrated Circuits and Systems Conference (MIXDES), Warsaw, Poland, pp. 45-50, (ISBN: 978-1-4577-2092-5) (2012)F. Javid, S. Youssef, R. Iskander, M.‑M. Louërat : “A Designer Centric Analog Synthesis Flow ”, Colloque GDR SOC-SIP, Paris, France, 1-2 pages (2012)Y. Li, R. Iskander, F. Javid, M.‑M. Louërat : “An Interface between System-level and Circuit-level for Design of Mixed-Signal Systems ”, Colloque GDR SOC-SIP, Paris, France, 1-2 pages (2012)
2011
S. Youssef, F. Javid, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Python-Based Layout-Aware Analog Design Methodology For Nanometric Technologies ”, IEEE 6th International Design and Test Workshop (IDT), Beyrouth, Lebanon, pp. 62-67 (2011)S. Youssef, F. Javid, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Seamless Representation for Coupling Transistor Sizing with Nanometric CMOS Layout Generation ”, 20th European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, pp. 341-344, (ISBN: 978-1-4577-0617-2) (2011)S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Stack-Based Routing Methodology For Nanometric Analogue CMOS Devices ”, The IEEE Virtual Worldwide Forum For PhD Researchers in Electronic Design Automation, (VW FEDA), Southampton, United Kingdom, pp. 1-6 (2011)S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Stack-Based Routing Methodology For Nanometric CMOS Devices ”, IEEE MOS-AK/GSA Workshop, Paris, FranceFrance, pp. 1-2 (2011)F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “Analog Circuits Sizing Using Bipartite Graphs ”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, South Korea, pp. 1-4, (ISBN: 1548-3746) (2011)R. Iskander, M.‑M. Louërat : “Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties ”, IEEE MOS-AK/GSA Workshop, Paris, FranceFrance, pp. 1-2 (2011)F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “Using Compact MOS Models for Hierarchical Sizing and Biasing of Analog IPs ”, IEEE MOS-AK/GSA Workshop, Paris, France, pp. 1-2 (2011)S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “Routing Methodology For Nanometric Analog CMOS Devices ”, Colloque GDR SOC SIP, Lyon, France, 1-2 pages (2011)
2010
S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Python-Based Analog Layout Generation Tool For Nanometer CMOS Technologies ”, Colloque national du GDR SOC-SIP, Cergy, France, pp. 1-2 (2010)S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “Automatic Stress Effects Computation Based On A Layout Generation Tool For Analog IC ”, 2010 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2010), San Jose, CA, USA, pp. 7-12, (IEEE) (2010)R. Khalil, A. Dudka, D. Galayko, R. Iskander, Ph. Basset : “Design and modeling of a successive approximation ADC for the electrostatic harvester of vibration energy ”, BMAS 2010 - IEEE International Behavioral Modeling and Simulation Conference, San Jose, USA, pp. 57-62, (IEEE) (2010)M. Kayal, R. Iskander, R. Castro‑Lopez : “Tutorial Session: Future Trends in Analog EDA ”, NEWCAS IEEE International Conference on NEWCAS, Montréal, Québec, Canada (2010)F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “A Design Environment for Analog IPs Design Knowledge Capture and Migration ”, Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, 1-2 pages (2010)R. Khalil, M. Allam, R. Iskander, M.‑M. Louërat : “Design and Modeling of 8-Bit Successive Approximation Analog to Digital Converter ”, Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, 1-2 pages (2010)
2009
R. Iskander, M.‑M. Louërat, A. Kaiser : “Design and Analysis of Analog Firm IPs using Hierarchical Sizing and Biasing Methodology ”, ESSDERC European Solid-State Device Research Conference, Athens, Greece, pp. 1-2 (2009)R. Iskander, M.‑M. Louërat, A. Kaiser : “Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties ”, DATE University Booth, Nice, France, pp. 1-2 (2009)F. Javid, R. Iskander, M.‑M. Louërat : “Simulation-Based Hierarchical Sizing and Biasing of Analog Firm IPs ”, IEEE International Behavioral Modeling and Simulation Conference (BMAS), San Jose, California, United States, pp. 43-48, (IEEE) (2009)
2008
R. Iskander, M.‑M. Louërat, A. Kaiser : “Automatic DC Operating Point Computation and Design Plan Generation for Analog IPs ”, Analog Integrated Circuits and Signal Processing, vol. 56 (1-2), pp. 93-105, (ISBN: 1573-1979) (2008)R. Iskander : “Synthèse de composants analogiques intégrès VLSI réutilisables ”, 博士论文, 答辩 2008-7-2, 责任导师 Louërat, Marie-Minerve, 助理责任导师 GREINER Alain (2008)
2007
R. Iskander, M.‑M. Louërat, A. Kaiser : “Computing Systematic Offsets in Amplifiers Using Hierarchical Graph-Based Sizing and Biasing ”, ICM International Conference on Microelectronics, Le Caire, Egypt, pp. 391-394, (IEEE) (2007)R. Iskander, M.‑M. Louërat, A. Kaiser : “Détection et évaluation des tensions de décalage d’un circuit analogique ”, TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Lyon, France, pp. 13-16 (2007)R. Iskander, M.‑M. Louërat, A. Kaiser, D. Galayko : “Knowledge-Aware Synthesis Using Hierarchical Graph-Based Sizing and Biasing ”, 50th Midwest Symposium on Circuits and Systems (MWSCAS), Montréal, Québec, Canada, pp. 984-987, (IEEE), (ISBN: 978-1-4244-1163-4) (2007)R. Iskander, A. Kaiser, M.‑M. Louërat : “Systematic Offset Detection and Evaluation Using Hierarchical Graph-Based Sizing and Biasing ”, 14th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Marrackech, Morocco, pp. 170-173, (IEEE) (2007)R. Iskander, D. Galayko, M.‑M. Louërat : “Connaissance et Opimisation pour la Synthèse Analogique ”, Colloque Groupement de Recherche : System-On-Chip, System-In-Package, GDR SoC SiP, Paris, France, 1-2 pages (2007)
2006
R. Iskander, M.‑M. Louërat, A. Kaiser : “Dimensionnement automatique d’un circuit analogique à l’aide des transistors de référence ”, TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Strasbourg, France, pp. 89-92 (2006)R. Iskander, M.‑M. Rosset‑Louërat, A. Kaiser : “Hierarchical Graph-Based Sizing for Analog Cells Through Reference Transistors ”, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics Winner of the Bronze Leaf Certificate, Otranto, Italy, pp. 321-324, (IEEE) (2006)D. Galayko, R. Iskander, M.‑M. Louërat, A. Greiner : “Réutilisation et migration d’amplificateurs avec CAIRO ”, JP CNFM Journées pédagogiques du CNFM, Saint Malo, France, pp. 35-39 (2006)R. Iskander, P. Nguyen‑Tuong, L. de Lamarre, V. Bourguet, M.‑M. Louërat, A. Greiner : “Automated Hierarchical Knowledge-Based Synthesis for Analog Cells using CAIRO ”, DATE University Booth, Munich, Allemagne (2006)
2005
R. Iskander, M.‑M. Rosset‑Louërat, A. Kaiser : “Automatic Biasing Point Extraction and Design Plan Generation for Analog IPs ”, MWSCAS 2005 - 48th Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, USA, pp. 907-910, (IEEE) (2005)R. Iskander, L. de Lamarre, P. Nguyen‑Tuong, M.‑M. Louërat, A. Kaiser : “Synthèse d’un IP amplificateur analogique CMOS avec CAIRO ”, TAISA 2005 - 6ème Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Marseille, France, pp. 69-72 (2005)
2004
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