Methodology for Substrate Parasitic Modeling in HV/HT Smart Power Technology - Application to Automotive Industry
Smart Power Integrated Circuits (ICs) are intensively used in automotive embedded systems due to their unique capabilities to merge low power and high voltage (HV) devices on the same chip. In such systems, induced electrical coupling noise due to switching of the power stages is a big issue. During switching, parasitic voltages and currents, lead to a local shift of the substrate potential that can reach hundreds of millivolts, and can severely disturb low voltage circuits. Such parasitic signals are known to represent the major cause of failure and costly circuit redesign in power ICs. Most solutions are layout dependent and are thus difficult to optimize using available electrical simulator. The lack for a model strategy prohibits an efficient design strategy and fails at giving clear predictions of perturbations in HV ICs. Here, we present a post-layout extraction and simulation methodology for substrate parasitic modeling. We have developed a Computer-Aided-Design (CAD) tool for substrate extraction from layout patterns. The extraction employs a meshing algorithm for substrate model generation. The behavior of the substrate currents can be taken into account in post-layout simulation, and enables an exhaustive failure analysis due to substrate coupling. Several industrial test cases are considered to validate this work, the interference of substrate currents in a current mirror configuration, and a standard automotive test in ams AG technology. This methodology is also applied to a HV BCD technology of STMicroelectronics. Eventually, by using the proposed CAD tool, it becomes possible to simulate the behaviors of substrate noises before fabrication.
H. Zou, Y. Moursy, R. Iskander, M.‑M. Louërat, J.‑P. Chaput : “A novel CAD framework for substrate modeling”, 10th Conference on Ph.D Research in Microelectronics and electronics, Grenoble, France, pp. 1-4, (IEEE) (2014)