LIP6 CNRS Sorbonne Université Tremplin Carnot Interfaces
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MOURSY Yasser

PhD graduated
Team : CIAN
Departure date : 05/31/2016
Supervision : Marie-Minerve LOUËRAT
Co-supervision : ISKANDER Ramy

A methodology for analysis and verification of the substrate noise coupling in HV/HT integrated circuits for automotive applications

Automotive application is a growing market for smart power integrated circuits (ICs). The smart power ICs miniaturize the electronic systems and improve their functionality for the vehicles. Product robustness and reliability in smart power ICs are vital aspects in automotive applications. However, failures due to substrate noise coupling are still reported in tests after fabrication. The sources of this noise are the injection of majority and minority carriers in the substrate. The majority carriers propagation is well modeled, however, the minority carriers propagation can not be modeled by the conventional modeling techniques.
In the first part of this work, we explore a new modeling technique proposed by a research group in EPFL. It relies on models that are capable of maintaining the minority carriers concentration and gradient. It allows the substrate parasitic extraction taking into account both majority and minority carriers. A CAD tool (AUTOMICS) is developed by our team in UPMC and is used to extract the substrate parasitic network encapsulating the new modeling technique.
In the second part of this work, we introduce a new methodology for smart power ICs design and failure analysis using the tool. It focuses on failures due to minority carriers coupling. The proposed methodology is validated on an industrial test case (AUTOCHIP1). This test case was designed in ams and validated by Valeo. This test case suffers from a latch-up problem. This problem is not recognized by conventional simulations. Using our methodology, we manage to reproduce the behavior in simulation environment.
The third part of this work presents system and circuit level design for a DC-DC buck converter. This system is considered as a complex system to validate our proposed methodology. The circuit was fabricated using 0.35 um HV-CMOS technology. The high voltage switches serve as aggressors injecting minority carriers in the substrate. An analog sensitive circuit, which is the bandgap, is considered as a victim. The effect of the substrate coupling is studied and simulation results show acceptable consistency with the measurements.
Defence : 05/20/2016 - 14h00 - Site Jussieu, Tour 55 2ème étage, couloir 55-65, salle 211
Jury members :
SOBOT Robert (ENSEA) [Rapporteur]
PILLONNET Gaël (CEA-LETI) [Rapporteur]
KAISER Andreas (ISEN)
ALLARD Bruno (INSA Lyon)
MEHREZ Habib (UPMC)
LOUËRAT Marie-Minerve (CNRS)
TISSERAND Pierre (Valeo)
ISKANDER Ramy (UPMC)

2013-2016 Publications

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