6 Doktoren 2012 - 2016

Publikationen 2004-2016

• 2016
  • Y. Moursy, H. Zou, R. Iskander, P. Tisserand, D.‑M. Ton, G. Pasetti, Eh. Seebacher, A. Steinmair, Th. Gneiting, H. Alius : “Towards Automatic Diagnosis of Minority Carriers Propagation Problems in HV/HT Automotive Smart Power ICs”, Design, Automation & Test in Europe Conference & Exhibition (DATE) 2016 Conference, Dresde, Germany (2016)
  • H. Zou, Y. Moursy, R. Iskander, J.‑P. Chaput, M.‑M. Louërat : “An Adaptive Mesh Refinement Strategy of Substrate Modeling for Smart Power ICs”, 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, pp. 2358-2361 (2016)
  • Y. Moursy, R. Khalil, S. Lecce, V. Poletto, R. Iskander, M.‑M. Louërat : “Mixed-Signal PI Controller in Current-Mode DC-DC Buck Converter for Automotive Applications”, IEEE International Symposium on Circuits and Systems (ISCAS'16), Montréal, Canada, pp. 1610-1613, (IEEE) (2016)
  • Y. Moursy, H. Zou, R. Khalil, R. Iskander, P. Tisserand, D.‑M. Ton, G. Pasetti, M.‑M. Louërat : “Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications”, IEEE Transactions on Power Electronics, (Institute of Electrical and Electronics Engineers) (2016)
  • H. Zou, Y. Moursy, R. Iskander, A. Steinmair, H. Gensinger, Eh. Seebacher, J.‑P. Chaput, M.‑M. Louërat : “Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology”, IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 2323-2333, (IEEE) (2016)
• 2015
  • R. Iskander, F. Javid, M.‑M. Louërat : “Is there a chance that computers understand analog design?”, 2^nd Workshop Design Automation for Understanding Hardware Designs (DUHDe), Grenoble, France (2015)
  • A. Malak, Y. Li, R. Iskander, F. Durbin, F. Javid, M.‑M. Louërat, A. Tissot, J.‑M. Guebhard : “Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations”, Integration, the VLSI Journal, vol. 48, pp. 198-212, (Elsevier) (2015)
  • H. Zou, Y. Moursy, R. Iskander, J.‑P. Chaput, M.‑M. Louërat, C. Stefanucci, P. Buccella, M. Kayal, J.‑M. Sallese, Th. Gneiting, H. Alius, A. Steinmair, Eh. Seebacher : “A CAD integrated solution of substrate modeling for industrial IC design”, 2015 20^th International Mixed-Signal Testing Workshop (IMSTW), Paris, France (2015)
  • Y. Moursy, R. Iskander, M.‑M. Louërat : “Automated triangular wave generator design with process corners compensation”, Mixed-Signal Testing Workshop (IMSTW), 2015 20^th International, Paris, France, pp. 1-6, (IEEE) (2015)
  • C. Stefanucci, P. Buccella, Y. Moursy, H. Zou, R. Iskander, M. Kayal, J.‑M. Sallese : “Substrate modeling to improve reliability of high voltage technologies”, 20^th International Mixed-Signal Testing Workshop (IMSTW), 2015, Paris, Paris, France (2015)
  • H. Zou, Y. Moursy, R. Iskander, C. Stefanucci, P. Buccella, M. Kayal, J.‑M. Sallese : “Substrate noise modeling with dedicated CAD framework for smart power ICs”, 2015 IEEE International Symposium on Circuits and Systems (ISCAS) n°1554, Lisbon, Portugal, pp. 4 (2015)
  • Y. Li, H. Zou, Y. Moursy, R. Iskander, R. Sobot, M.‑M. Louërat : “Optimization and Co-Simulation of an Implantable Telemetry System by Linking System Models to Nonlinear Circuits”, chapter in Computational Intelligence in Analog an Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, pp. 83-113, (Springer) (2015)
• 2014
  • Th. Vörtler, Th. Klotz, K. Einwich, Y. Li, Zh. Wang, M.‑M. Louërat, J.‑P. Chaput, F. Pêcheux, R. Iskander, M. Barnasconi : “Enriching UVM in SystemC with AMS extensions for randomization and coverage”, Design and Verification Conference and Exhibition (DVCON Europe), Munich, Germany (2014)
  • R. Lucas, E. Vaumorin, Ph. Cuenot, Y. Li, Zh. Wang, M.‑M. Louërat, J.‑P. Chaput, F. Pêcheux, R. Iskander, M. Barnasconi, Th. Vörtler, K. Einwich : “Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS extensions”, Design and Verification Conference and Exhibition (DVCON Europe), Munich, Germany (2014)
  • H. Zou, Y. Moursy, R. Iskander, M.‑M. Louërat, J.‑P. Chaput : “A novel CAD framework for substrate modeling”, 10^th Conference on Ph.D Research in Microelectronics and electronics, Grenoble, France, pp. 1-4, (IEEE) (2014)
  • Y. Li, R. Iskander, M.‑M. Louërat : “Modeling, Design and Verification Platform using SystemC AMS”, 15^th International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, United States, pp. 39-46, (IEEE) (2014)
  • Y. Li, Zh. Wang, M.‑M. Louërat, F. Pêcheux, R. Iskander, Ph. Cuenot, M. Barnasconi, Th. Vörtler, K. Einwich : “Virtual Prototyping, Verification and Validation Framework for Automotive Using SystemC, SystemC-AMS and SystemC-UVM”, Embedded Real Time Software and Systems (ERTS2), Toulouse, France, pp. 1-10 (2014)
  • Y. Li, R. Iskander, F. Javid, M.‑M. Louërat : “A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS”, chapter in Models, Methods, and Tools for Complex Chip Design, vol. 265, Lecture Notes in Electrical Engineering, pp. 89-108, (Springer) (2014)
• 2013
  • Y. Moursy, S. Afara, P. Buccella, C. Stefanucci, R. Iskander, M. Kayal, J.‑M. Sallese, M.‑M. Louërat, J.‑P. Chaput, M. Thomas Tomasevic , S. Ben Dhia, A. Boyer, B. Guegan, V. Poletto, A. Roggero, T. Cavioni, E. Novarini, Eh. Seebacher, A. Steinmair, P. Tisserand, D.‑M. Ton, Th. Bousquet, Th. Gneiting : “AUTOMICS: A novel approach for substrate modeling for Automotive applications”, 18^th IEEE European Test Symposium, Avignon, France (2013)
  • F. Javid, R. Iskander, M.‑M. Louërat, F. Durbin : “A Structured DC Analysis Methodology for Accurate Verification of Analog Circuits”, IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, pp. 2662-2665, (IEEE) (2013)
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Hierarchical sizing and biasing of analog firm intellectual properties”, Integration, the VLSI Journal, vol. 46 (2), pp. 172-188, (Elsevier) (2013)
  • F. Javid, S. Youssef, R. Iskander, M.‑M. Louërat : “A Designer-Assisted Analog Synthesis Flow”, chapter in Analog/RF and Mixed-Signal Circuit Systematic Design, vol. 233, Lecture Notes in Electrical Engineering, pp. 123-148, (Springer) (2013)
• 2012
  • F. Javid, R. Iskander, F. Durbin, M.‑M. Louërat : “Analog Circuits Sizing Using the Fixed Point Iteration Algorithm with Transistor Compact Models”, International Journal of Microelectronics and Computer Science, vol. 3 (1), pp. 7-14, (Department of Microelectronics and Computer Science (DMCS) of Technical University of Łódź) (2012)
  • Y. Li, R. Iskander, F. Javid, M.‑M. Louërat : “A Unified Platform for Design and Verification of Mixed-Signal Systems Based on SystemC-AMS”, Forum on specification & Design Languages, FDL 2012, Vienna, Austria, pp. 75-82 (2012)
  • F. Javid, S. Youssef, R. Iskander, M.‑M. Louërat : “A Designer Centric Analog Synthesis Flow”, Colloque GDR SOC-SIP, Paris, France, pp. 1-2 (2012)
  • Y. Li, R. Iskander, F. Javid, M.‑M. Louërat : “An Interface between System-level and Circuit-level for Design of Mixed-Signal Systems”, Colloque GDR SOC-SIP, Paris, France, pp. 1-2 (2012)
  • F. Javid, R. Iskander, F. Durbin, M.‑M. Louërat : “Analog Circuits Sizing Using the Fixed Point Iteration Algorithm with Transistor Compact Models”, 19^th IEEE International Mixed Design of Integrated Circuits and Systems Conference (MIXDES), Warsaw, Poland, pp. 45-50 (2012)
• 2011
  • F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “Analog Circuits Sizing Using Bipartite Graphs”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea, Republic of, pp. 1-4 (2011)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “Routing Methodology For Nanometric Analog CMOS Devices”, Colloque GDR SOC SIP, Lyon, France, pp. 1-2 (2011)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Stack-Based Routing Methodology For Nanometric CMOS Devices”, IEEE MOS-AK/GSA Workshop, Paris, France, pp. 1-2 (2011)
  • R. Iskander, M.‑M. Louërat : “Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties”, IEEE MOS-AK/GSA Workshop, Paris, France, pp. 1-2 (2011)
  • F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “Using Compact MOS Models for Hierarchical Sizing and Biasing of Analog IPs”, IEEE MOS-AK/GSA Workshop, Paris, France, pp. 1-2 (2011)
  • S. Youssef, F. Javid, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Python-Based Layout-Aware Analog Design Methodology For Nanometric Technologies”, IEEE 6^th International Design and Test Workshop (IDT), Beyrouth, Lebanon, pp. 62-67 (2011)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Stack-Based Routing Methodology For Nanometric Analogue CMOS Devices”, The IEEE Virtual Worldwide Forum For PhD Researchers in Electronic Design Automation, (VW FEDA), Southampton, United Kingdom, pp. 1-6 (2011)
  • S. Youssef, F. Javid, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Seamless Representation for Coupling Transistor Sizing with Nanometric CMOS Layout Generation”, 20^th European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, pp. 341-344 (2011)
• 2010
  • R. Khalil, A. Dudka, D. Galayko, R. Iskander, Ph. Basset : “Design and Modeling of a Successive Approximation ADC for the Electrostatic Harvester of Vibration Energy”, BMAS 2010 - IEEE International Behavioral Modeling and Simulation Conference, San Jose, United States, pp. 57-62, (IEEE) (2010)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Python-Based Analog Layout Generation Tool For Nanometer CMOS Technologies”, Colloque national du GDR SOC-SIP, Cergy, France, pp. 1-2 (2010)
  • F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “A Design Environment for Analog IPs Design Knowledge Capture and Migration”, Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, pp. 1-2 (2010)
  • R. Khalil, M. Allam, R. Iskander, M.‑M. Louërat : “Design and Modeling of 8-Bit Successive Approximation Analog to Digital Converter”, Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, pp. 1-2 (2010)
  • M. Kayal, R. Iskander, R. Castro‑Lopez : “Tutorial Session: Future Trends in Analog EDA”, NEWCAS IEEE International Conference on NEWCAS, Montréal, Québec, Canada (2010)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “Automatic Stress Effects Computation Based On A Layout Generation Tool For Analog IC”, 2010 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2010), San Jose, CA, United States, pp. 7-12 (2010)
• 2009
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Design and Analysis of Analog Firm IPs using Hierarchical Sizing and Biasing Methodology”, ESSDERC European Solid-State Device Research Conference, Athens, Greece, pp. 1-2 (2009)
  • F. Javid, R. Iskander, M.‑M. Louërat : “Simulation-Based Hierarchical Sizing and Biasing of Analog Firm IPs”, IEEE International Behavioral Modeling and Simulation Conference (BMAS), San Jose, California, United States, pp. 43-48, (IEEE) (2009)
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties”, DATE University Booth, Nice, France, pp. 1-2 (2009)
• 2008
  • R. Iskander : “Synthèse de composants analogiques intégrès VLSI réutilisables”, these, verteidigung einer doktorarbeit 02.07.2008, forschungsleitung (direction de recherche) Louërat, Marie-Minerve, co-betreuung : Greiner, Alain (2008)
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Automatic DC operating point computation and design plan generation for analog IPs”, Analog Integrated Circuits and Signal Processing, vol. 56 (1-2), pp. 93-105, (Springer Verlag) (2008)
• 2007
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Computing Systematic Offsets in Amplifiers Using Hierarchical Graph-Based Sizing and Biasing”, ICM International Conference on Microelectronics, Le Caire, Egypt, pp. 391-394, (IEEE) (2007)
  • R. Iskander, A. Kaiser, M.‑M. Louërat : “Systematic Offset Detection and Evaluation Using Hierarchical Graph-Based Sizing and Biasing”, 14^th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Marrackech, Morocco, pp. 170-173, (IEEE) (2007)
  • R. Iskander, M.‑M. Louërat, A. Kaiser, D. Galayko : “Knowledge-Aware Synthesis Using Hierarchical Graph-Based Sizing and Biasing”, 50^th Midwest Symposium on Circuits and Systems (MWSCAS), Montréal, Québec, Canada, pp. 984-987, (IEEE) (2007)
  • R. Iskander, D. Galayko, M.‑M. Louërat : “Connaissance et Optimisation pour la Synthèse Analogique”, Colloque Groupement de Recherche : System-On-Chip, System-In-Package, GDR SoC SiP, Paris, France, pp. 1-2 (2007)
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Détection et évaluation des tensions de décalage d’un circuit analogique”, TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Lyon, France, pp. 13-16 (2007)
• 2006
  • D. Galayko, R. Iskander, M.‑M. Louërat, A. Greiner : “Réutilisation et migration d’amplificateurs avec CAIRO+”, JP CNFM Journées pédagogiques du CNFM, Saint Malo, France, pp. 35-39 (2006)
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Dimensionnement automatique d’un circuit analogique à l’aide des transistors de référence”, TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Strasbourg, France, pp. 89-92 (2006)
  • R. Iskander, M.‑M. Rosset‑Louërat, A. Kaiser : “Hierarchical Graph-Based Sizing for Analog Cells Through Reference Transistors”, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics Winner of the Bronze Leaf Certificate, Otranto, Italy, pp. 321-324, (IEEE) (2006)
  • R. Iskander, P. Nguyen‑Tuong, L. De Lamarre, V. Bourguet, M.‑M. Louërat, A. Greiner : “Automated Hierarchical Knowledge-Based Synthesis for Analog Cells using CAIRO+”, Design Automation and Test in Europe Conference (DATE'2006), Munich, Germany (2006)
• 2005
  • R. Iskander, M.‑M. Rosset‑Louërat, A. Kaiser : “Automatic Biasing Point Extraction and Design Plan Generation for Analog IPs”, MWSCAS 2005 - 48^th Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, United States, pp. 907-910, (IEEE) (2005)
  • R. Iskander, L. De Lamarre, P. Nguyen‑Tuong, M.‑M. Louërat, A. Kaiser : “Synthèse d’un IP amplificateur analogique CMOS avec CAIRO+”, TAISA 2005 - 6^e Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Marseille, France, pp. 69-72 (2005)
• 2004
  • R. Iskander, L. De Lamarre, A. Kaiser, M.‑M. Rosset‑Louërat : “Design Space Exploration for Analog IPs using CAIRO+”, ICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Cairo, Egypt, pp. 473-476, (IEEE) (2004)