Bài báo khoa học 2015-2026

• 2026
  • V. Thomas, U. Zahid, G. Gambardella, Haralampos‑G. Stratigopoulos, B. Clerkin : “On the Efficacy of Vector Retrieval System under Hardware Faults”, 39^th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Rome, Italy (2026)
  • S. Raptis, Haralampos‑G. Stratigopoulos : “Adversarial Vulnerability of Neuromorphic Processors Demonstrated on Loihi Chip”, 2026 IEEE 8^th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Ha Long, Viet Nam (2026)
  • X. Zhang, I. Kaskampas, A. Pinna, Haralampos‑G. Stratigopoulos : “SNN2Bitstream: Automated Model-to-FPGA HLS-Based Framework for Spiking Neural Network Hardware Accelerators”, 2026 IEEE 8^th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Ha Long, Viet Nam (2026)
  • A. Emad Abdelazim, A. Díaz‑Rizo, H. Aboushady, Haralampos‑G. Stratigopoulos : “AI-Enabled Covert Channel Detection in RF Receiver Architectures”, Journal of Hardware and Systems Security, vol. 10 (1), pp. 20 (2026)
  • E. Dole, A. Emad Abdelazim, H. Aboushady, Haralampos‑G. Stratigopoulos, A. Díaz‑Rizo : “On-Chip AI-Driven Detection of Hardware Trojan-Based Covert Channels”, 2026 IEEE International Conference on Cyber Security and Resilience (CSR 2026), Lisbonne, Portugal (2026)
  • Zh. Song, Haralampos‑G. Stratigopoulos, H. Aboushady : “A Heterogeneous Neural Network Accelerator for End-to-End Multitask RF Signal Recognition”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-14, (IEEE) (2026)
  • H. Xuan, Z. Jouni, M. Manokhin, D. Galayko, Haralampos‑G. Stratigopoulos : “Automated Model-to-Transistor Design Framework for Memristor Crossbar-Based Spiking Neural Network Architectures”, IEEE International Joint Conference on Neural Networks (IJCNN 2026), Maasticht, Netherlands (2026)
  • S. Raptis, Haralampos‑G. Stratigopoulos : “Training-Free Intellectual Property Protection for Spiking Neural Networks”, IEEE International Joint Conference on Neural Networks (IJCNN 2026), Maasticht, Netherlands (2026)
  • S. Raptis, Haralampos‑G. Stratigopoulos : “Training Test Inputs for Spiking Neural Network Hardware: A Case Study on the Loihi 2 Neuromorphic Processor”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, (IEEE) (2026)
  • V. Thomas, U. Zahid, G. Gambardella, S. Sapkal, Haralampos‑G. Stratigopoulos, B. Clerkin : “Towards Resilient Transformer-Encoders: Fault Injection and Hardware Agnostic Error Mitigation”, 31^st IEEE European Test Symposium, Chania, Greece (2026)
  • A. Bayram, Haralampos‑G. Stratigopoulos, E. Afacan : “Co-Optimizing Performance and Security of Analog Integrated Circuits”, 2026 IEEE 29^th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Bratislava, Slovakia, (IEEE) (2026)
  • V. Barbaza, A. Díaz‑Rizo, A. Emad Abdelazim, E. Dole, H. Aboushady, S. Raptis, Haralampos‑G. Stratigopoulos : “Stealing AI Model Weights Through Covert Communication Channels”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-14, (IEEE) (2026)
  • A. Pagani, J. Cano, Haralampos‑G. Stratigopoulos, A. Abidin, Mh. Al Koutayni, L. Benini, A. Bilas, A. Capotondi, R. Cavicchioli, B. Clerkin, O. Deniz, M. Divernois, B. Dupertuis, D. Favre, G. Gambardella, A. Garcia Gangoiti, C. Grazia, D. Günzel, J. Haris, Klodjan K. Hidri, M. Huguenin, M. Jammal, P. Kling, Ch. Kozanitis, X. Lessage, S. Mandapati, Ph. Massonet, A. Di Mauro, V. Mishra, J. Odriozola, J. Parra Domínguez, N. Pazos, V. Potocnik, M. De Prado, R. Prasad, S. Raptis, G. Rebstein, I. Sañudo Olmedo, M. Selim, Ch. Shrivastav, N. Vallez, G. Vasiliadis, M. Verrucchi, E. Vincenzi, D. Vizár, D. Vyas, S. Wiehle : “Multi-Partner project: dAIEDGE - A network of excellence for distributed, trustworthy, efficient and scalable AI at the edge”, DATE B2026 - Design, Automation and Test in Europe Conference : The European Event for Electronic System Design & Test, Vérone, Italy (2026)
  • Zh. Song, Haralampos‑G. Stratigopoulos, H. Aboushady : “Edge-Efficient Transformer for End-to-End RF Spectrum Monitoring”, IEEE Transactions on Circuits and Systems II: Express Briefs, (Institute of Electrical and Electronics Engineers) (2026)
• 2025
  • G. Montoya‑Zúñiga, A. Díaz‑Rizo, H. Aboushady, R. Parra‑Michel, A. Veloz‑Guerrero, Haralampos‑G. Stratigopoulos : “Anti-Counterfeiting Design of Bluetooth Transceivers Through Logic Locking”, 2025 IEEE Global Communications Conference, Taipei, Taiwan, Province of China (2025)
  • Z. Jouni, Haralampos‑G. Stratigopoulos : “STDP-Trained Spiking Neural Network Reliability Assessment Through Fault Injections”, 31^st IEEE International Symposium on On-Line Testing and Robust System Design, Ischia, Italy (2025)
  • M. Jenihhin, J. Raik, A. Jutman, N. Cherezova, R. Ubar, L. Miclea, S. Enyedi, I. Stefan, O. Stan, C. Corches, Z. Peng, P. Eles, R. Drechsler, S. Eggersglüß, G. Fey, A. Glowatz, D. Tille, G. Gielen, A. Coyette, W. Dobbelaere, R. Vanhooren, P.‑Y. Chuang, E. Marinissen, G. Di Natale, M. Barragan, P. Maistri, S. Mir, I. Vatajelu, P. Bernardi, S. Di Carlo, P. Prinetto, M. Sonza Reorda, M. Violante, H. Stratigopoulos, Maria K. Michael, S. Neophytou, S. Hadjitheophanous, Kyriakos A. Christou, M. Skitsas, A. Bosio, B. Deveautour, P. Girard, M. Traiola, A. Virazel, F. Fernandes dos Santos, A. Kritikakou, G. Casagranda, M. Vallero, F. Vella, P. Rech, L. Bolzani Poehls, M. Krstic, M. Andjelkovic, F. Vargas, G. Tshagharyan, G. Harutyunyan, V. Vardanian, Samvel K. Shoukourian, Y. Zorian, J. Dworak, K. Nepal, Th. Manikas, M. Taouil, M. Fieback, A. Gebregiorgis, R. Bishnoi, S. Hamdioui, A. Chatterjee, A. Saha, S. Komarraju, K. Ma, Ch. Amarnath, Mehdi B. Tahoori, M. Mayahinia, M. Rajabalipanah, K. Basharkhah, N. Nosrati, Z. Jahanpeima, Z. Navabi, H.‑J. Wunderlich, S. Hellebrand : “European Test Symposium Teams : an Anniversary Snapshot”, 2025 IEEE European Test Symposium (ETS), Tallinn, Estonia, pp. 1-48, (IEEE), (ISBN: 979-8-3315-9450-3) (2025)
  • Th. Spyrou, H.‑G. Stratigopoulos, Ih. Alouani, S. Hamdioui, A. Gebregiorgis : “On the Trustworthiness of Spiking Neural Networks and Neuromorphic Systems”, 2025 IEEE European Test Symposium (ETS), Tallinn, Estonia, pp. 1-10, (IEEE), (ISBN: 979-8-3315-9450-3) (2025)
  • S. Raptis, Haralampos‑G. Stratigopoulos : “Input-Specific and Universal Adversarial Attack Generation for Spiking Neural Networks in the Spiking Domain”, International Joint Conference on Neural Networks (IJCNN), Rome, Italy (2025)
  • S. Sapkal, U. Zahid, G. Gambardella, Haralampos‑G. Stratigopoulos, B. Clerkin : “On the Fault Sensitivity of Natural Language Embeddings Computation”, 30^th IEEE European Test Symposium (ETS), Tallinn, Estonia (2025)
  • Zh. Song, A. Emad Abdelazim, P. Bazargan‑Sabet, F. Wajsbürt, Haralampos‑G. Stratigopoulos, H. Aboushady : “A Power-Efficient Attention-Infused CNN Hardware Accelerator for RF Spectrum Monitoring”, IEEE International Symposium on Circuits and Systems, London, United Kingdom (2025)
  • Hazem H. Hammam, H. Aboushady, Haralampos‑G. Stratigopoulos : “Anti-Counterfeiting Secured Design of a Bandgap Reference Circuit”, IEEE International Symposium on Circuits and Systems, London, United Kingdom (2025)
  • A. Díaz Rizo, H. Aboushady, Haralampos‑G. Stratigopoulos : “Live Demonstration: Securing Wireless ICs Against Supply Chain Attacks Using SyncLock”, IEEE International Symposium on Circuits and Systems, London, United Kingdom (2025)
  • S. Raptis, P. Kling, I. Kaskampas, Ih. Alouani, Haralampos‑G. Stratigopoulos : “Input-Triggered Hardware Trojan Attack on Spiking Neural Networks”, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), San Jose (CA), United States (2025)
  • A. Díaz Rizo, H. Aboushady, Haralampos‑G. Stratigopoulos : “Securing Wireless Integrated Circuits Against Supply Chain Attacks: SyncLock Demonstration”, (2025)
  • H. Hammam, H. Aboushady, Haralampos‑G. Stratigopoulos : “Analog Circuit Anti-Piracy Security by Exploiting Device Ratings”, Design, Automation & Test in Europe Conference (DATE), Lyon, France, (IEEE), (ISBN: 978-3-9826741-0-0) (2025)
  • S. Raptis, Haralampos‑G. Stratigopoulos : “Minimum Time Maximum Fault Coverage Testing of Spiking Neural Networks”, Design, Automation & Test in Europe Conference (DATE), Lyon, France, (IEEE), (ISBN: 978-3-9826741-0-0) (2025)
• 2024
  • Th. Spyrou, S. Hamdioui, Haralampos‑G. Stratigopoulos : “SpikeFI: A Fault Injection Framework for Spiking Neural Networks”, (2024)
  • H. Aboushady, N. Beringuier‑Boher, K. Burke, Ph. Dallemagne, M. De Biase, M. Di Frangia, V. Deniau, E. Ferrari, Ch. Gaquière, D. Morche, F. Patrone, S. Pesci, L. Pomante, A. Stam, V. Stornelli, Haralampos‑G. Stratigopoulos, M. Taouil, E. Vaumorin, J. Villain, S. Steeghs : “Trusted SMEs for Sustainable Growth of Europeans Economical Backbone to Strengthen the Digital Sovereignty: The KDT Resilient Trust Project”, 2024 27^th Euromicro Conference on Digital System Design (DSD), Paris, France, pp. 620-627, (IEEE) (2024)
  • A. Díaz Rizo, A. Emad Abdelazim, H. Aboushady, Haralampos‑G. Stratigopoulos : “Covert Communication Channels Based On Hardware Trojans: Open-Source Dataset and AI-Based Detection”, IEEE International Symposium on Hardware Oriented Security and Trust, Washington D.C., United States (2024)
  • N. Afroz, Ah. Sayem, G. Volanis, D. Maliuk, Haralampos‑G. Stratigopoulos, Y. Makris : “On the Sensitivity of Analog Artificial Neural Network Models to Process Variation”, 42^nd IEEE VLSI Test Symposium (VTS 2024), VTS24 proceedings, Tempe, AZ, United States (2024)
  • W. Guo, K. Yang, Haralampos‑G. Stratigopoulos, H. Aboushady, Kh. Salama : “An End-To-End Neuromorphic Radio Classification System with an Efficient Sigma-Delta-Based Spike Encoding Scheme”, IEEE Transactions on Artificial Intelligence, vol. 5 (4), pp. 1869-1881, (IEEE) (2024)
• 2023
  • Haralampos‑G. Stratigopoulos, Th. Spyrou, S. Raptis : “Testing and Reliability of Spiking Neural Networks: A Review of the State-of-the-Art”, 36^th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2023), Juan-Les-Pins, France (2023)
  • A. Díaz‑Rizo, H. Aboushady, Haralampos‑G. Stratigopoulos : “Leaking Wireless ICs via Hardware Trojan-Infected Synchronization”, IEEE Transactions on Dependable and Secure Computing, vol. 20 (5), pp. 3845-3859, (Institute of Electrical and Electronics Engineers) (2023)
  • Th. Spyrou, Haralampos‑G. Stratigopoulos : “On-Line Testing of Neuromorphic Hardware”, 2023 IEEE European Test Symposium (ETS), Venise, Italy, pp. 1-6, (IEEE), (ISBN: 979-8-3503-3634-4) (2023)
  • S. El‑Sayed, Th. Spyrou, L. Camuñas‑Mesa, Haralampos‑G. Stratigopoulos : “Compact Functional Testing for Neuromorphic Computing Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42 (7), pp. 2391-2403, (IEEE) (2023)
  • F. Su, Ch. Liu, Haralampos‑G. Stratigopoulos : “Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives”, IEEE Design & Test, vol. 40 (2), pp. 8-58, (IEEE) (2023)
  • A. Díaz‑Rizo, H. Aboushady, Haralampos‑G. Stratigopoulos : “Anti-Piracy Design of RF Transceivers”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70 (1), pp. 492-505, (IEEE) (2023)
  • Haralampos‑G. Stratigopoulos : “Machine Learning Support for Diagnosis of Analog Circuits”, chapter in Machine Learning Support for Fault Diagnosis of System-on-Chip, (Springer Nature) (2023)
• 2022
  • M. Portolan, A. Pavlidis, G. Di Natale, E. Faehn, Haralampos‑G. Stratigopoulos : “Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure”, 2022 IEEE International Test Conference (ITC), Anaheim, CA, United States, pp. 539-543, (IEEE), (ISBN: 978-1-6654-6270-9) (2022)
  • J. Leonhard, N. Limaye, Sh. Turk, A. Sayed, A. Díaz‑Rizo, H. Aboushady, O. Sinanoglu, Haralampos‑G. Stratigopoulos : “Digitally-Assisted Mixed-Signal Circuit Security”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41 (8), pp. 2449-2462, (IEEE) (2022)
  • A. Díaz Rizo, J. Leonhard, H. Aboushady, Haralampos‑G. Stratigopoulos : “RF Transceiver Security Against Piracy Attacks”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69 (7), pp. 3169-3173, (Institute of Electrical and Electronics Engineers) (2022)
  • A. Pavlidis, E. Faehn, M.‑M. Louërat, Haralampos‑G. Stratigopoulos : “Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs”, 40^th IEEE VLSI Test Symposium 2022, San Diego, United States, pp. 1-8, (IEEE) (2022)
  • Th. Spyrou, S. El‑Sayed, E. Afacan, L. Camuñas‑Mesa, B. Linares‑Barranco, Haralampos‑G. Stratigopoulos : “Reliability Analysis of a Spiking Neural Network Hardware Accelerator”, Design, Automation and Test in Europe Conference (DATE), Antwerp, Belgium, pp. 370-375, (IEEE) (2022)
  • A. Díaz Rizo, H. Aboushady, Haralampos‑G. Stratigopoulos : “SyncLock: RF Transceiver Security Using Synchronization Locking”, Design, Automation and Test in Europe Conference (DATE), Antwerp, Belgium, pp. 1153-1156, (IEEE) (2022)
  • M. Elshamy, G. Di Natale, A. Sayed, A. Pavlidis, M.‑M. Louërat, H. Aboushady, Haralampos‑G. Stratigopoulos : “Digital-to-Analog Hardware Trojan Attacks”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69 (2), pp. 573-586, (IEEE) (2022)
  • M. Tlili, A. Sayed, D. Mahmoud, M.‑M. Louërat, H. Aboushady, Haralampos‑G. Stratigopoulos : “Anti-Piracy of Analog and Mixed-Signal Circuits in FD-SOI”, 2022 27^th Asia and South Pacific Design Automation Conference (ASP-DAC), Virtual, Taiwan, Province of China, pp. 423-428, (IEEE) (2022)
• 2021
  • M. Elshamy, A. Sayed, M.‑M. Louërat, H. Aboushady, Haralampos‑G. Stratigopoulos : “Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29 (12), pp. 2130-2142, (IEEE) (2021)
  • M. Elshamy, Haralampos‑G. Stratigopoulos : “Neuron-PUF: Physical Unclonable Function Based on a Single Spiking Neuron”, 27^th IEEE International Symposium on On-Line Testing and Robust System Design, Virtual event, Italy, pp. 1-6, (IEEE) (2021)
  • A. Pavlidis, E. Faehn, M.‑M. Louërat, Haralampos‑G. Stratigopoulos : “BIST-Assisted Analog Fault Diagnosis”, 26^th IEEE European Test Symposium, Bruges (virtual), Belgium, pp. 1-6, (IEEE) (2021)
  • A. Pavlidis, M.‑M. Louërat, E. Faehn, A. Kumar, Haralampos‑G. Stratigopoulos : “SymBIST: Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68 (6), pp. 2580-2593, (IEEE) (2021)
  • Th. Spyrou, S. El‑Sayed, E. Afacan, L. Camuñas‑Mesa, B. Linares‑Barranco, Haralampos‑G. Stratigopoulos : “Neuron Fault Tolerance in Spiking Neural Networks”, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble (virtuel), France, pp. 743-748, (IEEE) (2021)
  • J. Leonhard, M. Elshamy, M.‑M. Louërat, Haralampos‑G. Stratigopoulos : “Breaking Analog Biasing Locking Techniques via Re-Synthesis”, 26^th Asia and South Pacific Design Automation Conference (ASPDAC '21), Tokyo, Japan (2021)
• 2020
  • S. El‑Sayed, Th. Spyrou, A. Pavlidis, E. Afacan, L. Camuñas‑Mesa, B. Linares‑Barranco, Haralampos‑G. Stratigopoulos : “Spiking Neuron Hardware-Level Fault Modeling”, 2020 IEEE 26^th International Symposium on On-Line Testing and Robust System Design (IOLTS), Naples, Italy (2020)
  • M. Elshamy, G. Di Natale, A. Pavlidis, M.‑M. Louërat, Haralampos‑G. Stratigopoulos : “Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism”, 2020 IEEE European Test Symposium (ETS), Tallinn, Estonia (2020)
  • M. Elshamy, A. Sayed, M.‑M. Louërat, A. Rhouni, H. Aboushady, Haralampos‑G. Stratigopoulos : “Securing Programmable Analog ICs Against Piracy”, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France (2020)
  • A. Pavlidis, M.‑M. Louërat, E. Faehn, A. Kumar, Haralampos‑G. Stratigopoulos : “Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP”, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France (2020)
  • J. Leonhard, M.‑M. Louërat, H. Aboushady, O. Sinanoglu, Haralampos‑G. Stratigopoulos : “Mixed-Signal IP Protection Against Piracy Based on Logic Locking”, 32. GI / GMM / ITG - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Ludwigsburg, Germany (2020)
  • A. Pavlidis, M.‑M. Louërat, E. Faehn, A. Kumar, Haralampos‑G. Stratigopoulos : “SymBIST: Symmetry-based Analog/Mixed-Signal BIST”, 32. GI / GMM / ITG - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Ludwigsburg, Germany (2020)
  • J. Leonhard, A. Sayed, M.‑M. Louërat, H. Aboushady, Haralampos‑G. Stratigopoulos : “Analog and Mixed-Signal IC Security Via Sizing Camouflaging”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (IEEE) (2020)
• 2019
  • J. Leonhard, M.‑M. Louërat, H. Aboushady, O. Sinanoglu, Haralampos‑G. Stratigopoulos : “Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application”, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Laussane, Switzerland, pp. 185-188, (IEEE) (2019)
  • S. Ali El‑Sayed, L. Camuñas‑Mesa, B. Linares‑Barranco, Haralampos‑G. Stratigopoulos : “Self-Testing Analog Spiking Neuron Circuit”, 16^th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2019), Lausanne, Switzerland, pp. 81-84, (IEEE) (2019)
  • J. Leonhard, M. Yasin, Sh. Turk, M. Nabeel, M.‑M. Louërat, R. Chotin‑Avot, H. Aboushady, O. Sinanoglu, Haralampos‑G. Stratigopoulos : “MixLock: Securing Mixed-Signal Circuits via Logic Locking”, Design, Automation and Test in Europe (DATE 2019), Proceedings of the 2019 Design, Automation and Test in Europe, Florence, Italy, pp. 84-89 (2019)
• 2018
  • Haralampos‑G. Stratigopoulos : “Machine learning applications in IC testing”, 2018 IEEE European Test Symposium (ETS), Bremen, Germany, pp. 1-10, (IEEE) (2018)
  • N. Shimizu, J. Akita, M.‑M. Louërat, Haralampos‑G. Stratigopoulos, J.‑P. Chaput, D. Galayko : “Open Source Hardware and EDA Tools for Analog/Mixed-Signal Design and Prototyping”, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, (IEEE) (2018)
  • D. Genius, M.‑M. Louërat, F. Pêcheux, L. Apvrille, Haralampos‑G. Stratigopoulos : “Modeling Heterogeneous Embedded Systems with TTool”, DUHDe 2018 — 5^th Workshop on Design Automation for Understanding Hardware Designs, Dresden, Germany (2018)
• 2017
  • Haralampos‑G. Stratigopoulos, Ch. Streitwieser : “Adaptive Test Flow for Mixed-Signal ICs”, IEEE 35^th VLSI Test Symposium, Las Vegas, United States, pp. 1-6, (IEEE) (2017)
  • Haralampos‑G. Stratigopoulos, Ch. Streitwieser : “Adaptive Test with Test Escape Estimation for Mixed-Signal ICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (IEEE) (2017)
  • A. Ahmadi, Haralampos‑G. Stratigopoulos, K. Huang, A. Nahar, B. Orr, M. Pas, J. Carulli, Y. Makris : “Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36 (12), pp. 2120-2133, (IEEE) (2017)
• 2016
  • Manuel J. Barragan, R. Alhakim, Haralampos‑G. Stratigopoulos, M. Dubois, S. Mir, H. Le‑Gall, N. Bhargava, A. Bal : “A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC”, IEEE Transactions on Circuits and Systems I: Regular Papers, (IEEE) (2016)
  • M. Andraud, Haralampos‑G. Stratigopoulos, E. Simeu : “One-Shot Non-Intrusive Calibration Against Process Variations for Analog/RF Circuits”, IEEE Transactions on Circuits and Systems I: Regular Papers, (IEEE) (2016)
  • Manuel J. Barragan, Haralampos‑G. Stratigopoulos, S. Mir, H. Le‑Gall, N. Bhargava, A. Bal : “Practical Simulation Flow for Evaluating Analog and Mixed-Signal Test Techniques”, IEEE Design & Test, (IEEE) (2016)
  • G. RENAUD, Manuel J. Barragan, A. Laraba, Haralampos‑G. Stratigopoulos, S. Mir, H. Le‑Gall, H. Naudet : “A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs”, Journal of Electronic Testing: : Theory and Applications, pp. 407-421, (Springer Verlag) (2016)
  • A. Ahmadi, Haralampos‑G. Stratigopoulos, A. Nahar, B. Orr, M. Pas, Y. Makris : “Harnessing fabrication process signature for predicting yield across designs”, IEEE International Symposium on Circuits and Systems, Montreal, Canada (2016)
  • Haralampos‑G. Stratigopoulos, B. Kaminska : “Analog and Mixed-Signal Test”, chapter in Electronic Design Automation for Integrated Circuits Handbook, (CRC Press) (2016)
  • A. Dimakos, Haralampos‑G. Stratigopoulos, A. Siligaris, S. Mir, E. De Foucauld : “Built-in test of millimeter-wave circuits based on non-intrusive sensors”, Design, Automation & Test in Europe Conference, Dresden, Germany (2016)
  • S. Hamdioui, M. Michael, G. Di Natale, Haralampos‑G. Stratigopoulos : “Proceedings of IEEE European Test Symposium (ETS 2016)”, ETS: European Test Symposium, Amsterdam, Netherlands, (IEEE) (2016)
• 2015
  • A. Ahmadi, Haralampos‑G. Stratigopoulos, A. Nahar, B. Orr, M. Pas, M. Yiorgos : “Yield forecasting in fab-to-fab production migration based on Bayesian Model Fusion”, IEEE/ACM International Conference on Computer-Aided Design, Austin, TX, United States, pp. 9-14, (IEEE) (2015)
  • Haralampos‑G. Stratigopoulos, Manuel J. Barragan, S. Mir, H. Le‑Gall, N. Bhargava, A. Bal : “Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times”, IEEE International Test Conference (ITC 2015), 2015 IEEE International Test Conference (ITC), Anaheim, CA, United States, (IEEE) (2015)
  • A. Dimakos, Haralampos‑G. Stratigopoulos, A. Siligaris, S. Mir, E. Foucauld : “Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors”, Journal of Electronic Testing: : Theory and Applications, vol. 31 (4), pp. 381–394, (Springer Verlag) (2015)
  • A. Laraba, Haralampos‑G. Stratigopoulos, S. Mir, H. Naudet : “Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62 (10), pp. 2391-2400, (IEEE) (2015)