2 PhD students (Supervision / Co-supervision)

• ABDELAZIM Abdelrahman : Design of an AI hardware accelerator for edge computing
• RAPTIS Spyridon : Architectures matérielles fiable pour l’Intelligence Artificielle de confiance

7 PhD graduated 2020 - 2023

2015-2023 Publications

• 2023
  • Th. Spyrou, Haralampos‑G. Stratigopoulos : “On-Line Testing of Neuromorphic Hardware”, 28^th IEEE European Test Symposium (ETS23), Venise, Italy (2023)
  • F. Su, Ch. Liu, Haralampos‑G. Stratigopoulos : “Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives”, IEEE Design & Test, (IEEE) (2023)
• 2022
  • A. Díaz‑Rizo, H.‑G. Stratigopoulos, H. Aboushady : “Leaking Wireless ICs via Hardware Trojan-Infected Synchronization”, IEEE Transactions on Dependable and Secure Computing, (Institute of Electrical and Electronics Engineers) (2022)
  • M. Portolan, A. Pavlidis, G. Di Natale, E. Faehn, Haralampos‑G. Stratigopoulos : “Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure”, IEEE International Test Conference, Anaheim, United States (2022)
  • J. Leonhard, N. Limaye, Sh. Turk, A. Sayed, A. Díaz‑Rizo, H. Aboushady, O. Sinanoglu, Haralampos‑G. Stratigopoulos : “Digitally-Assisted Mixed-Signal Circuit Security”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41 (8), pp. 2449-2462, (IEEE) (2022)
  • A. Díaz Rizo, J. Leonhard, H. Aboushady, Haralampos‑G. Stratigopoulos : “RF Transceiver Security Against Piracy Attacks”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69 (7), pp. 3169-3173, (Institute of Electrical and Electronics Engineers) (2022)
  • A. Pavlidis, E. Faehn, M.‑M. Louërat, Haralampos‑G. Stratigopoulos : “Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs”, 40^th IEEE VLSI Test Symposium 2022, San Diego, United States, pp. 1-8, (IEEE) (2022)
  • Th. Spyrou, S. El‑Sayed, E. Afacan, L. Camuñas‑Mesa, B. Linares‑Barranco, Haralampos‑G. Stratigopoulos : “Reliability Analysis of a Spiking Neural Network Hardware Accelerator”, Design, Automation and Test in Europe Conference (DATE), Antwerp, Belgium, pp. 370-375, (IEEE) (2022)
  • A. Díaz Rizo, H. Aboushady, Haralampos‑G. Stratigopoulos : “SyncLock: RF Transceiver Security Using Synchronization Locking”, Design, Automation and Test in Europe Conference (DATE), Antwerp, Belgium, pp. 1153-1156, (IEEE) (2022)
  • M. Tlili, A. Sayed, D. Mahmoud, M.‑M. Louërat, H. Aboushady, Haralampos‑G. Stratigopoulos : “Anti-Piracy of Analog and Mixed-Signal Circuits in FD-SOI”, 2022 27^th Asia and South Pacific Design Automation Conference (ASP-DAC), Virtual, Taiwan, Province of China, pp. 423-428, (IEEE) (2022)
  • A. Díaz‑Rizo, H. Aboushady, Haralampos‑G. Stratigopoulos : “Anti-Piracy Design of RF Transceivers”, IEEE Transactions on Circuits and Systems I: Regular Papers, (IEEE) (2022)
  • S. El‑Sayed, Th. Spyrou, L. Camuñas‑Mesa, H.‑G. Stratigopoulos : “Compact Functional Testing for Neuromorphic Computing Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (IEEE) (2022)
  • Haralampos‑G. Stratigopoulos : “Machine Learning Support for Diagnosis of Analog Circuits”, chapter in Machine Learning Support for Fault Diagnosis of System-on-Chip, (Springer) (2022)
• 2021
  • M. Elshamy, A. Sayed, M.‑M. Louërat, H. Aboushady, Haralampos‑G. Stratigopoulos : “Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29 (12), pp. 2130-2142, (IEEE) (2021)
  • M. Elshamy, G. Di Natale, A. Sayed, A. Pavlidis, M.‑M. Louërat, H. Aboushady, Haralampos‑G. Stratigopoulos : “Digital-to-Analog Hardware Trojan Attacks”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69 (2), pp. 573-586, (IEEE) (2021)
  • M. Elshamy, Haralampos‑G. Stratigopoulos : “Neuron-PUF: Physical Unclonable Function Based on a Single Spiking Neuron”, 27^th IEEE International Symposium on On-Line Testing and Robust System Design, Virtual event, Italy, pp. 1-6, (IEEE) (2021)
  • A. Pavlidis, E. Faehn, M.‑M. Louërat, Haralampos‑G. Stratigopoulos : “BIST-Assisted Analog Fault Diagnosis”, 26^th IEEE European Test Symposium, Bruges (virtual), Belgium, pp. 1-6, (IEEE) (2021)
  • A. Pavlidis, M.‑M. Louërat, E. Faehn, A. Kumar, Haralampos‑G. Stratigopoulos : “SymBIST: Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68 (6), pp. 2580-2593, (IEEE) (2021)
  • Th. Spyrou, S. El‑Sayed, E. Afacan, L. Camuñas‑Mesa, B. Linares‑Barranco, Haralampos‑G. Stratigopoulos : “Neuron Fault Tolerance in Spiking Neural Networks”, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble (virtuel), France, pp. 743-748, (IEEE) (2021)
  • J. Leonhard, M. Elshamy, M.‑M. Louërat, Haralampos‑G. Stratigopoulos : “Breaking Analog Biasing Locking Techniques via Re-Synthesis”, 26^th Asia and South Pacific Design Automation Conference (ASPDAC '21), Tokyo, Japan (2021)
• 2020
  • S. El‑Sayed, Th. Spyrou, A. Pavlidis, E. Afacan, L. Camuñas‑Mesa, B. Linares‑Barranco, Haralampos‑G. Stratigopoulos : “Spiking Neuron Hardware-Level Fault Modeling”, 2020 IEEE 26^th International Symposium on On-Line Testing and Robust System Design (IOLTS), Naples, Italy (2020)
  • M. Elshamy, G. Di Natale, A. Pavlidis, M.‑M. Louërat, Haralampos‑G. Stratigopoulos : “Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism”, 2020 IEEE European Test Symposium (ETS), Tallinn, Estonia (2020)
  • M. Elshamy, A. Sayed, M.‑M. Louërat, A. Rhouni, H. Aboushady, Haralampos‑G. Stratigopoulos : “Securing Programmable Analog ICs Against Piracy”, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France (2020)
  • A. Pavlidis, M.‑M. Louërat, E. Faehn, A. Kumar, Haralampos‑G. Stratigopoulos : “Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP”, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France (2020)
  • J. Leonhard, M.‑M. Louërat, H. Aboushady, O. Sinanoglu, Haralampos‑G. Stratigopoulos : “Mixed-Signal IP Protection Against Piracy Based on Logic Locking”, 32. GI / GMM / ITG - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Ludwigsburg, Germany (2020)
  • A. Pavlidis, M.‑M. Louërat, E. Faehn, A. Kumar, Haralampos‑G. Stratigopoulos : “SymBIST: Symmetry-based Analog/Mixed-Signal BIST”, 32. GI / GMM / ITG - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Ludwigsburg, Germany (2020)
  • J. Leonhard, A. Sayed, M.‑M. Louërat, H. Aboushady, Haralampos‑G. Stratigopoulos : “Analog and Mixed-Signal IC Security Via Sizing Camouflaging”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (IEEE) (2020)
• 2019
  • J. Leonhard, M.‑M. Louërat, H. Aboushady, O. Sinanoglu, Haralampos‑G. Stratigopoulos : “Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application”, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Laussane, Switzerland, pp. 185-188, (IEEE) (2019)
  • S. Ali El‑Sayed, L. Camuñas‑Mesa, B. Linares‑Barranco, Haralampos‑G. Stratigopoulos : “Self-Testing Analog Spiking Neuron Circuit”, 16^th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2019), Lausanne, Switzerland, pp. 81-84, (IEEE) (2019)
  • J. Leonhard, M. Yasin, Sh. Turk, M. Nabeel, M.‑M. Louërat, R. Chotin‑Avot, H. Aboushady, O. Sinanoglu, Haralampos‑G. Stratigopoulos : “MixLock: Securing Mixed-Signal Circuits via Logic Locking”, Design, Automation and Test in Europe (DATE 2019), Proceedings of the 2019 Design, Automation and Test in Europe, Florence, Italy, pp. 84-89 (2019)
• 2018
  • Haralampos‑G. Stratigopoulos : “Machine learning applications in IC testing”, 2018 IEEE European Test Symposium (ETS), Bremen, Germany, pp. 1-10, (IEEE) (2018)
  • N. Shimizu, J. Akita, M.‑M. Louërat, Haralampos‑G. Stratigopoulos, J.‑P. Chaput, D. Galayko : “Open Source Hardware and EDA Tools for Analog/Mixed-Signal Design and Prototyping”, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, (IEEE) (2018)
  • D. Genius, M.‑M. Louërat, F. Pêcheux, L. Apvrille, Haralampos‑G. Stratigopoulos : “Modeling Heterogeneous Embedded Systems with TTool”, DUHDe 2018 — 5^th Workshop on Design Automation for Understanding Hardware Designs, Dresden, Germany (2018)
• 2017
  • Haralampos‑G. Stratigopoulos, Ch. Streitwieser : “Adaptive Test Flow for Mixed-Signal ICs”, IEEE 35^th VLSI Test Symposium, Las Vegas, United States, pp. 1-6, (IEEE) (2017)
  • Haralampos‑G. Stratigopoulos, Ch. Streitwieser : “Adaptive Test with Test Escape Estimation for Mixed-Signal ICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (IEEE) (2017)
  • A. Ahmadi, Haralampos‑G. Stratigopoulos, K. Huang, A. Nahar, B. Orr, M. Pas, J. Carulli, Y. Makris : “Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36 (12), pp. 2120-2133, (IEEE) (2017)
• 2016
  • Manuel J. Barragan, R. Alhakim, Haralampos‑G. Stratigopoulos, M. Dubois, S. Mir, H. Le‑Gall, N. Bhargava, A. Bal : “A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC”, IEEE Transactions on Circuits and Systems I: Regular Papers, (IEEE) (2016)
  • M. Andraud, Haralampos‑G. Stratigopoulos, E. Simeu : “One-Shot Non-Intrusive Calibration Against Process Variations for Analog/RF Circuits”, IEEE Transactions on Circuits and Systems I: Regular Papers, (IEEE) (2016)
  • Manuel J. Barragan, Haralampos‑G. Stratigopoulos, S. Mir, H. Le‑Gall, N. Bhargava, A. Bal : “Practical Simulation Flow for Evaluating Analog and Mixed-Signal Test Techniques”, IEEE Design & Test, (IEEE) (2016)
  • G. RENAUD, Manuel J. Barragan, A. Laraba, Haralampos‑G. Stratigopoulos, S. Mir, H. Le‑Gall, H. Naudet : “A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs”, Journal of Electronic Testing: : Theory and Applications, pp. 407-421, (Springer Verlag) (2016)
  • A. Ahmadi, Haralampos‑G. Stratigopoulos, A. Nahar, B. Orr, M. Pas, Y. Makris : “Harnessing fabrication process signature for predicting yield across designs”, IEEE International Symposium on Circuits and Systems, Montreal, Canada (2016)
  • Haralampos‑G. Stratigopoulos, B. Kaminska : “Analog and Mixed-Signal Test”, chapter in Electronic Design Automation for Integrated Circuits Handbook, (CRC Press) (2016)
  • A. Dimakos, Haralampos‑G. Stratigopoulos, A. Siligaris, S. Mir, E. De Foucauld : “Built-in test of millimeter-wave circuits based on non-intrusive sensors”, Design, Automation & Test in Europe Conference, Dresden, Germany (2016)
  • S. Hamdioui, M. Michael, G. Di Natale, Haralampos‑G. Stratigopoulos : “Proceedings of IEEE European Test Symposium (ETS 2016)”, ETS: European Test Symposium, Amsterdam, Netherlands, (IEEE) (2016)
• 2015
  • A. Ahmadi, Haralampos‑G. Stratigopoulos, A. Nahar, B. Orr, M. Pas, M. Yiorgos : “Yield forecasting in fab-to-fab production migration based on Bayesian Model Fusion”, IEEE/ACM International Conference on Computer-Aided Design, Austin, TX, United States, pp. 9-14, (IEEE) (2015)
  • Haralampos‑G. Stratigopoulos, Manuel J. Barragan, S. Mir, H. Le‑Gall, N. Bhargava, A. Bal : “Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times”, IEEE International Test Conference (ITC 2015), 2015 IEEE International Test Conference (ITC), Anaheim, CA, United States, (IEEE) (2015)
  • A. Dimakos, Haralampos‑G. Stratigopoulos, A. Siligaris, S. Mir, E. Foucauld : “Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors”, Journal of Electronic Testing: : Theory and Applications, vol. 31 (4), pp. 381–394, (Springer Verlag) (2015)
  • A. Laraba, Haralampos‑G. Stratigopoulos, S. Mir, H. Naudet : “Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62 (10), pp. 2391-2400, (IEEE) (2015)