Recently, the enormous cost of owning and maintaining a modern semiconductor manufacturing plant has coerced many companies to go fabless. By outsourcing the manufacturing of integrated circuit/intellectual property (IC/IP) to third-party and often off-shore companies, the process has been extended to potentially untrustworthy companies. This has resulted in several security threats to the semiconductor industry such as counterfeiting, reverse engineering, and hardware Trojans (HTs) insertion. In this thesis, we propose an anti-piracy countermeasure to protect analog and mixed-signal (AMS) ICs/IPs, a novel HT attack for AMS ICs/IPs, and a novel physical unclonable function (PUF).
More specifically, we propose an anti-piracy technique based on locking for programmable analog circuits. The proposed technique leverages the programmability fabric to implement a natural lock-less locking. We discuss its implementation and its resilience capabilities against foreseen attacks, and we demonstrate it with simulation analysis and hardware measurements of programmable Sigma-Delta Analog-to-Digital Converters (ADCs) intended for use in highly-digitized, multi-standard RF receiver applications. The proposed HT attack for analog circuits leverages the test infrastructure. The HT is hidden effectively in a digital core and transfers its payload to the analog circuit via the test bus and the interface of the analog circuit to the test bus. Its key characteristic is that it is invisible in the analog domain. The proposed HT is demonstrated on two case studies. The first case study shown with simulation is a low-dropout (LDO) regulator and the second case study shown with hardware measurements is a programmable RF receiver front-end. This thesis sheds light on the importance of developing new security and trust countermeasures tailored for analog circuits. The proposed locking technique illustrates the feasibility of securing a large number of analog circuits while keeping their design intact, which is a crucial requirement for analog designers, in order for the locking technique to be widely adopted. For the proposed HT, it reveals the possibility of digital-to-analog HT attacks. The proposed PUF, called "neuron-PUF", uses a single spiking neuron as the source of entropy. Its key characteristic is that it uses a single PUF cell and temporal redundancy to generate an arbitrarily long key, which results in significant low area and power overheads compared to mainstream PUFs, such as delay-based and memory-based PUFs