Direction de recherche : Habib MEHREZ
Architectures matérielles pour l'arithmétique stochastique discrète
Voir rapport de recherche
Soutenance : 06/06/2003
Membres du jury :
Alain Guyot - rapporteur
Jean-Michel Muller - rapporteur
Jean Vignes
Jean-Luc Lamotte
Eric Martin
Alain Greiner
Habib Mehrez
Date de départ : 31/12/2003
Publications 2000-2023
Toutes
Articles de revues
Communications
Posters
Soutenance de thèse
2023
J. Fontaine, M. Benazouz, L. Zaourar, R. Chotin : “Improving Integrated Circuit Security using Mathematical Model Based on Clique Covering Reformulation ”, 9th International Conference on Control, Decision and Information Technologies (CoDiT 2023), 9th International Conference on Control, Decision and Information Technologies, Rome, Italy, pp. 1717-1722, (IEEE) (2023)
2022
I. Bournias, R. Chotin, L. Lacassagne : “Using HLS for Designing a Parametric Optical Flow Hierarchical Algorithm in FPGAs ”, IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, United States (2022)D. Genius, R. Chotin : “Model to Hardware : System-Level Modeling for Wearable Devices ”, ModelsWARD, Virtual Conference, France (2022)J. Fontaine, L. Zaourar, M. Benazouz, R. Chotin : “Recherche de cliques pour un problème de cybersécurité matériel ”, 23e édition du congrès annuel de la Société Française de Recherche Opérationnelle et d'Aide à la Décision, Villeurbanne, France (2022)
2021
N. Rambaux, J. Vaubaillon, S. Derelle, M. Jacquart, M. Millet, L. Lacassagne, A. Petreto, P. Simoneau, K. Baillié, J. Desmars, D. Galayko, R. Chotin : “Meteorix camera tests for space-based meteor observations ”, WGN, Journal of the International Meteor Organization, vol. 49 (5), pp. 142-144, (International Meteor Organization) (2021)N. Rambaux, J. Vaubaillon, S. Derelle, M. Jacquart, M. Millet, L. Lacassagne, A. Petreto, P. Simoneau, K. Baillié, J. Desmars, D. Galayko, R. Chotin : “Meteorix: A cubesat mission dedicated to the detection of meteors and space debris ”, International Meteor Conference (IMC), Paris, France (2021)J. Fontaine, L. Zaourar, R. Chotin : “Mathematical modelling of Logic Locking against the insertion of Hardware Trojan in an Intregated Circuit ”, 31 European conference on operational research, Athènes, Greece (2021)G. Rocherolle, R. Chotin : “Toward an Implementation Modeling Methodology for Designing SCA resilient Cryptographic Circuits ”, 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Montpellier, France, pp. 1-4, (IEEE) (2021)I. Bournias, R. Chotin, L. Lacassagne : “FPGA Acceleration of the Horn and Schunck Hierarchical algorithm ”, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, Republic of, (IEEE) (2021)J. Fontaine, L. Zaourar, R. Chotin : “Optimisation de contre-mesure à l’insertion de Hardware Trojan ”, 22e Conférence ROADEF de la société Française de Recherche Opérationnelle et Aide à la Décision, Mulhouse, France (2021)J. Cathébras, R. Chotin : “A HDL Generator for Flexible and Efficient Finite-Field Multipliers on FPGAs ”, WAIFI 2020 - 8th International Workshop on Arithmetic of Finite Fields, vol. 12542, Lecture Notes in Computer Science, Rennes, France, pp. 75-91, (Springer International Publishing) (2021)D. Genius, I. Bournias, L. Apvrille, R. Chotin : “Model-Based Virtual Prototyping of CPS: Application to Bio-Medical Devices ”, International Conference on Model-Driven Engineering and Software Development, vol. 1361, CCIS, Valletta, Malta, pp. 74-96, (Springer, Cham) (2021)
2020
F. Pêcheux, L. Andrade Porras, M.‑M. Louërat, I. Bournias, R. Chotin, D. Genius : “Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions ”, 2020 Forum for Specification and Design Languages (FDL), Kiel, Germany, pp. 1-8, (IEEE) (2020)D. Genius, I. Bournias, L. Apvrille, R. Chotin : “High-level Partitioning and Design Space Exploration for Cyber Physical Systems ”, Proceedings of the 8th International Conference on Model-Driven Engineering and Software Development - Volume 1: MODELSWARD, Valletta, Malta, pp. 84-91, (SCITEPRESS) (2020)
2019
J.‑P. Chaput, M.‑M. Louërat, R. Chotin‑Avot, A. Satin : “RISC-V design using Free Open Source Software ”, the RISC-V Week, Paris, France (2019)J. Leonhard, M. Yasin, Sh. Turk, M. Nabeel, M.‑M. Louërat, R. Chotin‑Avot, H. Aboushady, O. Sinanoglu, Haralampos‑G. Stratigopoulos : “MixLock: Securing Mixed-Signal Circuits via Logic Locking ”, Design, Automation and Test in Europe (DATE 2019), Proceedings of the 2019 Design, Automation and Test in Europe, Florence, Italy, pp. 84-89 (2019)
2018
2016
R. Chotin‑Avot : “Contributions à l’exploration d’architectures matérielles et au prototypage rapide ”, habilitation à diriger des recherches, soutenance 21/06/2016 (2016)M. Azeem, R. Chotin‑Avot, U. Farooq, M. Ravoson, H. Mehrez : “Multiple FPGAs based prototyping and debugging with complete design flow ”, IDT 2016 - 11th International Design & Test Symposium, Hammamet, Tunisia, pp. 171-176, (IEEE) (2016)U. Farooq, R. Chotin‑Avot, M. Azeem, M. Ravoson, H. Mehrez : “Inter-FPGA Routing Environment for Performance Exploration of Multi-FPGA Systems ”, Rapid System Prototyping (RSP), Pittsburgh, United States, pp. 1-6 (2016)U. Farooq, R. Chotin‑Avot, M. Azeem, Z. Cherif, M. Ravoson, S. Khan, H. Mehrez : “Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration ”, Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, pp. 641-645, (IEEE) (2016)K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs ”, Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, Prague, Czechia, pp. 37-40, (ACM) (2016)K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations ”, Journal of Signal Processing Systems, pp. 1-12, (Springer) (2016)
2014
A. Blanchardon, R. Chotin‑Avot, H. Mehrez, E. Amouri : “Impact of defect tolerance techniques on the criticality of a SRAM-based Mesh of Cluster FPGA ”, ReConFig 2014 - International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) (2014)A. Blanchardon, R. Chotin‑Avot, H. Mehrez, E. Amouri : “Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy ”, FPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Munich, Germany, pp. 1-4, (IEEE) (2014)K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Authenticated Encryption on FPGAs from the Static Part to the Reconfigurable Part ”, Microprocessors and Microsystems: Embedded Hardware Design, vol. 38 (6), pp. 526-538, (Elsevier) (2014)S.‑U. Rehman, A. Blanchardon, A. Ben Dhia, M. Benabdenbi, R. Chotin‑Avot, L. Naviner, L. Anghel, H. Mehrez, E. Amouri, Z. Marrakchi : “Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA ”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), Tampa, FL, United States, pp. 553-558, (IEEE) (2014)J. Chae, P. Mougeat, J.‑A. Francois, R. Chotin‑Avot, H. Mehrez : “A reference-based specification tool for creating reliable library development specifications ”, 12th International New Circuits and Systems Conference, NEWCAS 2014, Trois-Rivieres, QC, Canada, pp. 133-136, (IEEE) (2014)K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm ”, 10th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications, ARC 2014, vol. 8405, Lecture Notes in Computer Science, Vilamoura, Portugal, pp. 13-24, (Springer) (2014)J. Chae, P. Mougeat, J.‑A. Francois, R. Chotin‑Avot, H. Mehrez : “A formalism of the specifications for library development ”, IEEE International System-on-Chip Conference, Erlangen, Germany, pp. 307-312, (IEEE) (2014)K. Moussa Ali Abdellatif, R. Chotin‑Avot, Z. Marrakchi, H. Mehrez, Q. Tang : “Towards high performance GHASH for pipelined AES-GCM using FPGAs ”, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, United States, pp. 242-242, (ACM) (2014)K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Low cost Solutions for Secure Remote Reconfiguration of FPGAs ”, International Journal of Embedded Systems, vol. 6 (2-3), pp. 257-265, (Inderscience) (2014)
2013
J. Chae, S. Bertrand, P.‑F. Ollagnon, P. Mougeat, J.‑A. Francois, R. Chotin‑Avot, H. Mehrez : “Efficient State-Dependent Power Model for Multi-bit Flip-Flop Banks ”, IEEE International Midwest Symposium on Circuits and Systems, Columbus, United States, pp. 461-464, (IEEE) (2013)K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Improved Method for Parallel AES-GCM Cores Using FPGAs ”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-4, (IEEE) (2013)K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Lightweight and Compact Solutions for Secure Reconfiguration of FPGAs ”, International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-4, (IEEE) (2013)S. Belloeil, R. Chotin‑Avot, H. Mehrez : “Exploring redundant arithmetics in computer-aided design of arithmetic datapaths ”, Integration, the VLSI Journal, vol. 46 (2), pp. 104-118, (Elsevier) (2013)E. Amouri, A. Blanchardon, R. Chotin‑Avot, H. Mehrez, Z. Marrakchi : “Efficient Multilevel Interconnect Topology for Cluster-based Mesh FPGA Architecture ”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) (2013)A. Ben Dhia, S. Ur Rehman, A. Blanchardon, L. Naviner, M. Benabdenbi, R. Chotin‑Avot, H. Mehrez, E. Amouri, Z. Marrakchi : “A Defect-tolerant Cluster in a Mesh SRAM-based FPGA ”, International Conference on Field-Programmable Technology (FPT), Kyoto, Japan, pp. 434-437, (IEEE Computer Society) (2013)K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “High Speed Authenticated Encryption for Slow Changing Key Applications Using Reconfigurable Devices ”, Wireless Days (WD), 2013 IFIP, Valencia, Spain, pp. 1-6 (2013)K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Protecting FPGA Bitstreams Using Authenticated Encryption ”, 11th IEEE International Conference of New Circuits and Systems (NEWCAS), Paris, France, pp. 1-4, (IEEE) (2013)J. Chae, P. Mougeat, J.‑A. Francois, R. Chotin‑Avot, H. Mehrez : “Formalisme de la spécification de la plateforme de conception pour le développement de la bibliothèque ”, Journees Nationales du Reseau Doctoral de Micro-electronique, Grenoble, France, pp. 1-4 (2013)
2012
K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Efficient Parallel-Pipelined GHASH for Message Authentication ”, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2012), Cancun, Mexico, pp. 1-6 (2012)K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “The Effect of S-box Design on Pipelined AES Using FPGAs ”, Colloque GDR SOC-SIP, Paris, France, pp. 1-4 (2012)F. Hamzaoui, R. Chotin‑Avot, P. Renault, H. Mehrez, H. Belmabrouk, M. Machhout : “Synthesis and Optimization of Quantum Boolean Circuit Using the Truth Table Method ”, International Workshop on Number Theory, Codes, Cryptography and Communication Systems (NTCCCS), Oujda, Morocco, pp. 192-197 (2012)A. Blanchardon, R. Chotin‑Avot, H. Mehrez : “Générateur d’Architecture de FPGA ”, Colloque GDR SOC-SIP, Paris, France, pp. 1-3 (2012)
2011
Z. Guitouni, R. Chotin‑Avot, M. Machhout, H. Mehrez, R. Tourki : “High Performances ASIC Based Elliptic Curve Cryptographic Processor over GF(2m) ”, International Journal of Computer Applications, vol. Special Issue on Network Security and Cryptography (NSC) (4), pp. 1-10, (Foundation of Computer Science) (2011)F. Hamzaoui, R. Chotin‑Avot, M. Machhout, H. Mehrez, H. Belmabrouk : “Quantum circuits design and simulation ”, The First International Conference on "Research to Applications & Markets" (RAM 2011), Monastir, Tunisia, pp. 115-115 (2011)S. Belloeil, R. Chotin‑Avot, H. Mehrez : “Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools ”, ISQED 2011 - 12th International Symposium on Quality Electronic Design, Santa Clara, CA, United States, pp. 502-507, (IEEE) (2011)
2010
F. Hamzaoui, B. Othmani, R. Chotin‑Avot, M. Machhout, H. Belmabrouk, H. Mehrez : “Modélisation et simplification de circuits quantiques ”, Materiaux 2010, Mahdia, Tunisia, pp. 2-2 (2010)Z. Guitouni, R. Chotin‑Avot, M. Machhout, H. Mehrez, R. Tourki : “Design and FPGA Implementation of Modular Multiplication Methods Using Cellular Automata ”, DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Hammamet, Tunisia, pp. 1-5, (IEEE) (2010)
2008
S. Belloeil, R. Chotin‑Avot, H. Mehrez, A. Munier‑Kordon : “Automatic Allocation of Redundant Operators in Arithmetic Data path Optimization ”, DASIP IEEE International Conference on Design and Architectures for Signal and Image Processing, Bruxelles, Belgium, pp. 176-183 (2008)S. Belloeil, R. Chotin‑Avot, H. Mehrez : “Arithmetic Data path Optimization using Borrow-Save Representation ”, ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI, Montpellier, France, pp. 4-9, (IEEE) (2008)
2007
2006
A. Greiner, F. Pétrot, M. Carrier, M. Benabdenbi, R. Chotin‑Avot, R. Labayrade : “MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation ”, 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'06), Montpellier, France, pp. 24-30, (Université Montpellier II) (2006)A. Greiner, F. Pétrot, M. Carrier, M. Benabdenbi, R. Chotin‑Avot, R. Labayrade : “Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chip ”, IV 2006 - IEEE Intelligent Vehicles Symposium, Tokyo, Japan, pp. 370-376, (IEEE) (2006)S. Belloeil, J.‑P. Chaput, R. Chotin‑Avot, Ch. Masson, H. Mehrez : “Stratus : Un environnement de développement de circuits ”, JP CNFM Journées pédagogiques du CNFM, Saint-Malo, France, pp. 57-61 (2006)
2004
2003
R. Chotin : “Architectures matérielles pour l’arithmétique stochastique discrète ”, soutenance de thèse, soutenance 06/06/2003, direction de recherche Mehrez, Habib (2003)R. Chotin‑Avot : “Architectures matérielles pour l’arithmétique stochastique discrète ”, soutenance de thèse, soutenance 06/06/2003, direction de recherche Mehrez, Habib (2003)R. Chotin‑Avot, J.‑M. Chesneaux, J.‑L. Lamotte : “On the computation of the CESTAC function ”, Real Numbers and Computers 5 (RNC5), Lyon, France, pp. 247-260 (2003)R. Chotin‑Avot, H. Mehrez : “Hardware implementation of discrete stochastic arithmetic ”, 6th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'03), Poznan, Poland, pp. 57-64 (2003)
2002
R. Chotin, H. Mehrez : “A Floating-Point Unit using stochastic arithmetic compliant with the IEEE-754 standard ”, 9th IEEE International Conference on Electronics Circuits and Systems (ICECS'2002), Dubrovnik, Croatia, pp. 603-606 (2002)R. Chotin, H. Mehrez : “Hardware implementation of the CESTAC method ”, 10th GAMM - IMACS International Symposium on Scientific Computing Computer Arithmetic and Validated Numerics (SCAN'2002), Paris, France, pp. 162-162 (2002)R. Chotin, H. Mehrez : “Hardware implementation of a method to control round-off errors ”, 6th WSEAS International Multiconference on Circuits Systems Communications and Computers (CSCC'2002), Rethymnon, Greece, pp. 157-162 (2002)R. Chotin, H. Mehrez : “Implantation matérielle d’une méthode de contrôle des erreurs d’arrondi de calcul ”, Troisième colloque du GDR CAO de circuits et systèmes intégrés, Paris, France, pp. 63-66 (2002)R. Chotin, H. Mehrez : “Une unité de calcul flottant utilisant l’arithmétique stochastique ”, Vèmes Journées Nationales du Réseau Doctoral de Micro-électronique (JNRDM'2002), Grenoble, France, pp. 217-218 (2002)
2000