Contributions to hardware architectures exploration and rapid prototyping
The Internet of Things (IoT) is one of the fastest growing trends of the 21st century. In the next 10 years it is expected that, 150 billions of small physical objects will be connected to each other through the internet. A connected object is in fact a system with small form factor whose design is becoming increasingly complex requiring better energy efficiency. Moreover, given the pressing time-to-market targets in industry, designing such efficient systems becomes increasingly tedious and challenging. To ease the task of the designer, it is necessary to propose tools that allow exploring different hardware architectures to quickly develop a prototype that meets the required specifications. These tools help the designer to automate parts of the design process by exploring various criteria. They also allow him to make the appropriate choice for establishing the final prototype.
The work presented herein provides a framework to assist in prototyping and exploration of digital architectures. It is based on a library of generic IPs and evaluation functions that allows exploring different hardware solutions, in order to choose the one that satisfies best the specifications. This framework was employed to study architectures for redundant arithmetic, for authenticated encryption, and for FPGAs that are tolerant to manufacturing defects. Each time, the framework was used to study these architectures aiming at optimizing them according to standard criteria, such as size, frequency, power consumption, and reliability.
First, the proposed framework and its library of IPs are described. The different characteristics of the framework are detailed and guidelines for its general use are given. Then, different cases of application are presented. The first case considered is the performance improvement of arithmetic data paths using redundant arithmetic by implementing specific optimization algorithms. The second case involves the design of architectures for authenticated encryption that meet different needs in terms of throughput or size. Finally, the last case explores different FPGA topologies to reduce the interconnect size. Then, this architecture is evaluated in terms of reliability to manufacturing defects and solutions are proposed to improve the reliability.
In terms of future work, it is needed to continue developing this framework to make it capable of exploring efficient architectures in advanced technologies for various other applications and search for advantageous solutions. Moreover, this work also shows the need to integrate into the design flow new criteria, such as the reliability, and take them into consideration as early as in the design exploration phase together with the standard performance criteria.
Defence : 06/21/2016 - 10h30 - Site Jussieu 25-26/105
Jury members :
M. Florent de Dinechin, Professeur, INSA Lyon [Rapporteur]
M. Matteo Sonza Reorda, Professeur, Politecnico di Torino [Rapporteur]
M. Arnaud Tisserand, Directeur de Recherche CNRS, IRISA [Rapporteur]
Mme Lirida Naviner, Professeur, Telecom ParisTech
M. Guy Gogniat, Professeur, Lab-STICC
M. Jean-Claude Bajard, Professeur, LIP6
M. Habib Mehrez, Professeur, LIP6