LIP6 1998/005
- Thesis
Outils de vérification pour circuits VLSI AsGa MESFET par des méthodes d'abstraction fonctionnelle - P. Rémy
- 120 pages - 03/16/1998- document en - http://www.lip6.fr/lip6/reports/1998/lip6.1998.005.ps.gz - 296 Ko
- Contact : Pascal.Remy (at) nulllip6.fr
- Ancien Thème : ASIM
- Keywords : Gallium Arsenide integrated circuits, DCFL E/D MESFET circuits, Functional abstraction, Electrical verification, Functional verification, Timing verification, Pattern recognition
- Publisher : Francois.Dromard (at) nulllip6.fr
As part of this PhD, a verification environment for GaAs MESFET circuits has been developed. It is based on an oriented gates representation of the circuit obtained through functional abstraction of its transistor net-list representation. To obtain this representation, purely algorithmic methods but also pattern recognition methods have been used.
This representation is the starting point for the verification tools also developed as part of this PhD. The verifications involved are of electrical, functional and timing nature. Unlike CMOS circuits, GaAs MESFET circuits are very sensitive to transistor sizing errors that can cause malfunctions. The electrical verification tool automatically indicates any electrical rule violation amongst a pre-established set of rules. It uses parameters that can be modified and is upgradable. The functional verification tool supplies a VHDL model from the mask extracted transistor net-list. Finally the timing verification tool defines timing models for each oriented gate. The circuit's critical path as well as it's propagation delays are then obtained from these models.
This environment has been used to validate the GaAs MESFET circuits that have been devised at MASI laboratory these past years. Experimentation accomplished on circuits of various sizes demonstrates the linear complexity of the algorithms used. The overall results show that the adopted method enables us to deal with circuits of various sizes and of significant complexity.
This representation is the starting point for the verification tools also developed as part of this PhD. The verifications involved are of electrical, functional and timing nature. Unlike CMOS circuits, GaAs MESFET circuits are very sensitive to transistor sizing errors that can cause malfunctions. The electrical verification tool automatically indicates any electrical rule violation amongst a pre-established set of rules. It uses parameters that can be modified and is upgradable. The functional verification tool supplies a VHDL model from the mask extracted transistor net-list. Finally the timing verification tool defines timing models for each oriented gate. The circuit's critical path as well as it's propagation delays are then obtained from these models.
This environment has been used to validate the GaAs MESFET circuits that have been devised at MASI laboratory these past years. Experimentation accomplished on circuits of various sizes demonstrates the linear complexity of the algorithms used. The overall results show that the adopted method enables us to deal with circuits of various sizes and of significant complexity.