LIP6 2000/026
- Thesis
Simulation de Fautes et Optimisation des Tests de Production pour les Circuits Analogiques avec prise en compte des Tolérances - A. Khouas
- 173 pages - 09/14/2000- document en - http://www.lip6.fr/lip6/reports/2000/lip6.2000.026.ps.gz - 415 Ko
- Contact : Abdelhakim.Khouas (at) nulllip6.fr
- Ancien Thème : ASIM
- Keywords : VLSI, Analog Testing, Fault Detection, Fault Simulation, ATPG, Test Optimization, Process variations, Parameter deviations, Production Testing
- Publisher : Francois.Dromard (at) nulllip6.fr
As a result of the evolution of VLSI circuit density, analog circuits become more complex and more difficult to test, which requires automatic tools for both circuit test and diagnosis. This thesis presents a new methodology for fault simulation and automatic optimization of production tests of analog integrated circuits taking into account circuit parameter variations due to IC process fluctuations. The fault simulator is an essential tool for the development of any test strategy. It permits to verify the design for testability technique (DFT), and to reduce the cost of production tests. The two major characteristics of a fault simulator are: accuracy and rapidity. In order to satisfy the accuracy requirement in the analog world where component parameters are imprecise and are usually defined with tolerances, we have defined a fault detection probability function (PDF) which allows to quantify the degree of possible detection of a given fault. For the speed, we have proposed a new algorithm which uses stop rules to reduce simulation time. Due to the nature of analog circuits, the type of test depend on the circuit under test. It is thus impossible to develop an automatic test pattern generator for all types of circuits. That's why we have studied the problem of automatic optimization of an existing set of tests. In order to take into account process fluctuations, a method of production test optimization based on the fault detection probability function has been presented. A prototype of a CAD tool intended for fault simulation and automatic production test optimization has been developed so as to be able to verify our approach, the tool uses the electrical simulator __it ELDO_. This prototype has allowed us to verify our method, based on the fault detection probability function, on several circuits, and the obtained results are very promising.