LIP6 1999/026
- Thesis
Analyse sémantique de descriptions VHDL synchrones en vue de la synthèse - L. Jacomme
- 255 pages - 10/29/1999- document en - http://www.lip6.fr/lip6/reports/1999/lip6.1999.026.ps.gz - 625 Ko
- Contact : Ludovic.Jacomme (at) nulllip6.fr
- Ancien Thème : ASIM
- Keywords : Hardware description language, VHDL, compilation, semantic analysis, hardware synthesis
- Publisher : Francois.Dromard (at) nulllip6.fr
The VHDL hardware description language was initially defined to be used for simulation. It has been accepted as a standard for the behavioral specification of digital circuits for more than ten years. Quite naturally VHDL was quickly used as an input language for synthesis applications. However, due to its strong simulation semantic, the use of VHDL for synthesis appears to be a difficult problem. To avoid taking into account the complex language semantic during the compilation step, all synthesis tools enforce the use of specific templates to identify hardware elements in VHDL descriptions. Using such templates has clearly two drawbacks_: they restrict the style of description and the power of the language, and they affect seriously the portability of the language because they depend on the synthesis environment used. In this thesis we propose an opposite approach to the identification of the hardware elements. Our method relies exclusively on the simulation semantics and thus ensures post-synthesis results compliant with the VHDL simulation. A software based on this semantic analysis method has been developed. It has enabled us to show the efficiency of our method as much from a qualitative and quantitative point of view.