SHAN Chuan : Génération d'horloge distribuée pour Systèmes sur Puce .
2006
PALUS Maxime : Étude et validation de l'architecture d'une machine java de hautes performances .
2006-2019 Publications
2019
D. Galayko, Ch. Shan, E. Zianbetov, M. Javidan, A. Korniienko, O. Billoint, F. Anceau, E. Colinet, E. Blokhina, J. Juillard : “Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66 (10), pp. 1673-1677, (Institute of Electrical and Electronics Engineers) (2019)
F. Anceau : “La Saga des machines-langage et -système”, Cahiers d'histoire du Cnam, vol. vol.07 - 08 (2), La recherche sur les systèmes : des pivots dans l’histoire de l’informatique, pp. pp41-52, (Cnam) (2017)
D. Galayko, E. Blokhina, E. Zianbetov, A. Dudka, F. Anceau, E. Colinet, A. Korniienko, J. Juillard, Ph. Basset : “Complexity in heterogeneous systems on chips: Design and analysis challenges”, Proc. of the IEEE International Symposium on Circuits and Systems, Melbourne, Australia, pp. 1997-2000, (IEEE) (2014)
E. Zianbetov, D. Galayko, F. Anceau, M. Javidan, Ch. Shan, O. Billoint, A. Korniienko, E. Colinet, G. Scorletti, J.‑M. Akre, J. Juillard : “Distributed clock generator for synchronous SoC using ADPLL network”, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San José, CA, United States, pp. 1-4, (IEEE) (2013)
M. Javidan, E. Zianbetov, F. Anceau, D. Galayko, A. Korniienko, E. Colinet, G. Scorletti, J.‑M. Akre, J. Juillard : “All-digital PLL array provides reliable distributed clock for SOCs”, Proceedings of the 2011 IEEE International Symposium of Circuits and Systems, Rio de Janeiro, Brazil, pp. 2589-2592, (IEEE) (2011)
E. Zianbetov, M. Javidan, F. Anceau, D. Galayko, E. Colinet, J. Juillard : “Design and VHDL Modeling of All-Digital PLLs”, 8th IEEE International NEWCAS Conference (NEWCAS'10), Montreal, Canada, pp. 293-296, (IEEE) (2010)