Supervision : François ANCEAU

Co-supervision : GALAYKO Dimitri

Distributed Clock Generation for Large Synchronous SOCs.

This thesis addresses the problem of global synchronization in large system on chip (SoC). It focuses on the study of an alternative clock generation technique to conventional clock distribution and asynchronous communication. It allows implementation of highly reliable synchronous circuit.
My PhD project aims to study and implement a large network (10x10) of all digital phase-locked loop (ADPLL), containing 100 nodes generating a clock for each local digital circuitry. Several prototypes were designed, modeled and tested, including one implemented in 65nm CMOS technlogy, generating clocks in the range 903-1161 MHz. It highlights a maximum phase error of less than 40 ps between two clocks in any neighboring zones.
In order to validate the performance of synchronization in ASIC, we designed an on-chip clocking error measurement circuit. This circuit has a low rate for the off-chip readout (several MHz), and a high resolution (+-2 ps).

2011-2019 Publications

• 2019
  • D. Galayko, Ch. Shan, E. Zianbetov, M. Javidan, A. Korniienko, O. Billoint, F. Anceau, E. Colinet, E. Blokhina, J. Juillard : “Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66 (10), pp. 1673-1677, (Institute of Electrical and Electronics Engineers) (2019)
• 2016
  • K. Eugene, E. Blokhina, Ch. Shan, E. Zianbetov, O. Feely, D. Galayko : “Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks”, New Circuits and Systems Conference (NEWCAS), 2016 14^th IEEE International, Vancouver, BC, Canada (2016)
• 2015
  • Ch. Shan, E. Zianbetov, F. Anceau, O. Billoint, D. Galayko : “A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs”, New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13^th International, Grenoble, France (2015)
• 2014
  • Ch. Shan : “Génération d’horloge distribuée pour Systèmes sur Puce”, thesis, phd defence 11/14/2014, supervision Anceau, François, co-supervision : Galayko, Dimitri (2014)
  • Ch. Shan, D. Galayko, F. Anceau, E. Zianbetov : “A reconfigurable distributed architecture for clock generation in large many-core SoC”, Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9^th International Symposium on, Montpellier, France, pp. 1-8, (IEEE) (2014)
  • Ch. Shan, F. Anceau, D. Galayko, E. Zianbetov : “Swimming pool like distributed architecture for clock generation in large many-core SoC”, {IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014, Melbourne, Australia, pp. 2768-2771 (2014)
• 2013
  • Ch. Shan, E. Zianbetov, W. Yu, F. Anceau, O. Billoint, D. Galayko : “FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation”, Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, Cancun, Mexico, pp. 1-6 (2013)
  • E. Zianbetov, D. Galayko, F. Anceau, M. Javidan, Ch. Shan, O. Billoint, A. Korniienko, E. Colinet, G. Scorletti, J.‑M. Akre, J. Juillard : “Distributed clock generator for synchronous SoC using ADPLL network”, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San José, CA, United States, pp. 1-4, (IEEE) (2013)
  • Ch. Shan, D. Galayko, F. Anceau : “On-chip clock error characterization for clock distribution system”, VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on, Natal, Brazil, pp. 102-108 (2013)
• 2012
  • Ch. Shan, D. Galayko, F. Anceau : “Design and Modeling of ADPLL with sliding-window for wide range frequency tracking”, New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10^th International, Montreal, Canada, pp. 269-272 (2012)
• 2011
  • Ch. Shan, E. Zianbetov, M. Javidan, F. Anceau, M. Terosiet, S. Feruglio, D. Galayko, O. Romain, E. Colinet, J. Juillard : “FPGA implementation of reconfigurable ADPLL network for distributed clock generation”, FTP 2011 - International Conference on Field Programmable Technology, New Delhi, India, pp. 1-4, (IEEE) (2011)