Annuaire

ANCEAU François

Professeur Émérite
Équipe : CIAN
https://association-imag.fr/wp-content/uploads/2021/01/Francois-Anceau-1940-220.pdf

Date de départ : 30/09/2019

Deux docteurs (2006 - 2014) à Sorbonne Université

Publications 2006-2019

2019
- D. Galayko, Ch. Shan, E. Zianbetov, M. Javidan, A. Korniienko, O. Billoint, F. Anceau, E. Colinet, E. Blokhina, J. Juillard : “Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66 (10), pp. 1673-1677, (Institute of Electrical and Electronics Engineers) (2019)
2018
- F. Anceau, D. Etiemble : “Processeurs superscalaires "flots de données"”, (2018)
2017
- F. Anceau : “La Saga des machines-langage et -système”, Cahiers d'histoire du Cnam, vol. vol.07 - 08 (2), La recherche sur les systèmes : des pivots dans l’histoire de l’informatique, pp. pp41-52, (Cnam) (2017)
2015
- D. Etiemble, F. Anceau : “Processeurs superscalaires multi-pipelines”, Techniques de l'Ingenieur, (Techniques de l'ingénieur) (2015)
- Ch. Shan, E. Zianbetov, F. Anceau, O. Billoint, D. Galayko : “A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs”, New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13^th International, Grenoble, France (2015)
2014
- D. Galayko, E. Blokhina, E. Zianbetov, A. Dudka, F. Anceau, E. Colinet, A. Korniienko, J. Juillard, Ph. Basset : “Complexity in heterogeneous systems on chips: Design and analysis challenges”, Proc. of the IEEE International Symposium on Circuits and Systems, Melbourne, Australia, pp. 1997-2000, (IEEE) (2014)
- Ch. Shan, D. Galayko, F. Anceau, E. Zianbetov : “A reconfigurable distributed architecture for clock generation in large many-core SoC”, Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9^th International Symposium on, Montpellier, France, pp. 1-8, (IEEE) (2014)
- D. Etiemble, F. Anceau : “Hiérarchie mémoire : mémoire virtuelle”, Techniques de l'Ingenieur, (Techniques de l'ingénieur) (2014)
- Ch. Shan, F. Anceau, D. Galayko, E. Zianbetov : “Swimming pool like distributed architecture for clock generation in large many-core SoC”, {IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014, Melbourne, Australia, pp. 2768-2771 (2014)
2013
- Ch. Shan, E. Zianbetov, W. Yu, F. Anceau, O. Billoint, D. Galayko : “FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation”, Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, Cancun, Mexico, pp. 1-6 (2013)
- E. Zianbetov, D. Galayko, F. Anceau, M. Javidan, Ch. Shan, O. Billoint, A. Korniienko, E. Colinet, G. Scorletti, J.‑M. Akre, J. Juillard : “Distributed clock generator for synchronous SoC using ADPLL network”, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San José, CA, United States, pp. 1-4, (IEEE) (2013)
- D. Etiemble, F. Anceau : “Processeurs : exécution pipeline des instructions”, Techniques de l'Ingenieur, (Techniques de l'ingénieur) (2013)
- Ch. Shan, D. Galayko, F. Anceau : “On-chip clock error characterization for clock distribution system”, VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on, Natal, Brazil, pp. 102-108 (2013)
2012
- D. Etiemble, F. Anceau : “Hiérarchie mémoire : les caches”, Techniques de l'Ingenieur, (Techniques de l'ingénieur) (2012)
- Ch. Shan, D. Galayko, F. Anceau : “Design and Modeling of ADPLL with sliding-window for wide range frequency tracking”, New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10^th International, Montreal, Canada, pp. 269-272 (2012)
2011
- Ch. Shan, E. Zianbetov, M. Javidan, F. Anceau, M. Terosiet, S. Feruglio, D. Galayko, O. Romain, E. Colinet, J. Juillard : “FPGA implementation of reconfigurable ADPLL network for distributed clock generation”, FTP 2011 - International Conference on Field Programmable Technology, New Delhi, India, pp. 1-4, (IEEE) (2011)
- M. Javidan, E. Zianbetov, F. Anceau, D. Galayko, A. Korniienko, E. Colinet, G. Scorletti, J.‑M. Akre, J. Juillard : “All-digital PLL array provides reliable distributed clock for SOCs”, Proceedings of the 2011 IEEE International Symposium of Circuits and Systems, Rio de Janeiro, Brazil, pp. 2589-2592, (IEEE) (2011)
- E. Zianbetov, M. Javidan, F. Anceau, D. Galayko, E. Colinet, J. Juillard : “A 2GHz CMOS DCO with optimized architecture for high speed clocking”, Proceedings of International Symposium on Circuits and Systems (ISCAS'11), Rio de Janeiro, Brazil, pp. 2845-2848 (2011)
- E. Zianbetov, F. Anceau, M. Javidan, D. Galayko, E. Colinet, J. Juillard : “A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation”, ISCAS 2011 - IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, pp. 2845-2848, (IEEE) (2011)
- M. Javidan, E. Zianbetov, F. Anceau, D. Galayko, E. Colinet, J. Juillard : “A novel technique to reduce the metastability of Bang-Bang Phase Frequency Detectors”, International Symposium on Circuits and Systems (ISCAS'11), Rio de Janeiro, Brazil, pp. 2577-2580 (2011)
2010
- F. Anceau, D. Etiemble : “Introduction à l’architecture des ordinateurs”, Techniques de l'Ingenieur, (Techniques de l'ingénieur) (2010)
- E. Zianbetov, M. Javidan, F. Anceau, D. Galayko, E. Colinet, J. Juillard : “Design and VHDL Modeling of All-Digital PLLs”, 8^th IEEE International NEWCAS Conference (NEWCAS'10), Montreal, Canada, pp. 293-296, (IEEE) (2010)
2007
- F. Anceau, Y. Bonnassieux : “Conception de circuits VLSI. Du composant au système”, 315 pages, (Dunod), (ISBN: 978-2-10-050036-9) (2007)
- F. Anceau : “Past, Present and Future of Microprocessors”, chapter in Design of Systems on a Chip, Design and Test, pp. 65-82, (Springer), (ISBN: 978-0-387-32499-9) (2007)
2006
- M. Palus, F. Anceau : “JMQ, un processeur Java de hautes performances”, SympA Symposium en Architecture de Machines, Perpignan, France, pp. 154-165 (2006)