Méthodogie de conception d'architectures VLSI génériques appliquée au traitement numérique

Publicações 1997-1998

• 1998
  • M. Aberbour, A. Houelle, H. Mehrez, N. Vaucher, A. Guyot : “On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6 (1), pp. 114-121, (IEEE) (1998)
• 1997
  • N. Vaucher : “Méthodogie de conception d’architectures VLSI génériques appliquée au traitement numérique”, tese, defesas 20/06/1997, direção de pesquisa Mehrez, Habib (1997)
  • A. Guyot, S.‑J. Abou‑Samra, M. Aberbour, A. Houelle, H. Mehrez, N. Vaucher : “Modelling and synthesis of optimal adders under left-to-right input arrival”, IFIP International Workshop on Logic and Architecture Synthesis (IWLAS'97), Grenoble, France, (IFIP) (1997)
  • M. Aberbour, A. Houelle, H. Mehrez, N. Vaucher, A. Guyot : “A time driven adder generator architecture”, 9^th IFIP International Conference on Very Large Scale Integration (VLSI'97), Gramado, RS, Brazil, pp. 453-463, (Springer) (1997)
  • M. Aberbour, A. Derieux, H. Mehrez, N. Vaucher : “Teaching the design of a chip under the Cadence Opus environment using the Alliance cell libraries”, MSE '97 - IEEE International Conference on Microelectronic Systems Education, Arlington, VA, United States, pp. 81-82, (IEEE Computer Society) (1997)