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LIP6 1997/026

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    Méthodologie de conception d'architectures VLSI génériques appliquée au traitement numérique
  • N. Vaucher
  • 188 pages - 10/16/1997- document en - http://www.lip6.fr/lip6/reports/1997/lip6.1997.026.ps.tar.gz - 2,633 Ko
  • Contact : Nicolas.Vaucher (at) nullasim.lip6.fr
  • Ancien Thème : ASIM
  • In this thesis we present a design methodology of arithmetic operators generators, based on the use of a standard cells library. This methodology has been implemented in a tool, called GenOptim, aiding in the design of macro-block generators. The original issue in GenOptim is the "virtual" cell concept which allows the design of technology portable VLSI blocks. The goal of the GenOptim tool is to alleviate the designer from the technology related problems but enhancing the performances of the generated circuit by performing electrical and placement optimizations. This methodology has been used successfully in the design of arithmetic operators like integer addition, multiplication, division and square root. The original contribution lies in the design of a delay adaptive architecture adder, a generator of arborescent Wallace structures for the design of multipliers, as well as redundant division and square root operators. We also developed floating point operators complying to the IEEE-754 standard. But, in the design of an ASIC dedicated to signal processing it is not necessary that these operators be fully compliant to the IEEE-754 standard. Consequently, we developed modulable addition and multiplication floating point generators, in order to enhance the performances of these operators. Using the arithmetic generators, we designed a convolution circuit, called C8D32. This chip was designed to be used in a pattern recognition system in which the Gabor wavelets are used along with other optimization methods to extract the pertinent information in the image. The convolution chip computes the filtering of the image by a set of Gabor wavelets. The architecture of this chip is composed essentially of a systolic operator containing 8 elementary processors. The C8D32 is able to convolve images with 32 x 8 masks. The chip is cascadable so as to allow convolutions with larger kernels. Finally, the GenOptim design environment makes this chip portable over different technologies.
  • Keywords : technology portability, standard cells library, arithmetic algorithms and operators, optimized architecture synthesis, IEEE floating point operators, convolution
  • Publisher : Francois.Dromard (at) nulllip6.fr
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