BUKOVJAN Peter

毕业博士() - ASIM
离开日期 : 2000-10-1

责任导师 : Meryem MARZOUKI
助理责任导师 : BRZOBOHATY J.

Recherche de compromis coût/qualité dans un processus de synthèse en vue de la testabilité

答辩 : 2000-9-28 - Université Pierre et Marie Curie (UPMC)

1998-2001 刊物

所有刊物文章会议文章博士论文

2001
- P. Bukovjan, L. Ducerf‑Bourbon, M. Marzouki : “Cost/Quality Trade-Off in Synthesis for BIST”, Journal of Electronic Testing, vol. 17 (2), pp. 109-119, (ISBN: 0923-8174) (2001)
2000
- P. Bukovjan, L. Ducerf‑Bourbon, M. Marzouki : “Cost/Quality Trade-off in Synthesis for BIST”, 1^st IEEE Latin America Test Workshop (LATW), Rio de Janeiro, Brazil, pp. 110-115 (2000)
- P. Bukovjan, L. Ducerf‑Bourbon, M. Marzouki : “Cost/Quality Trade-off in Synthesis for Scan”, 3^rd International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Slomenice, Slovakia (2000)
- L. Ducerf‑Bourbon, P. Bukovjan, M. Marzouki : “TACOS: A Testability Allocation and Control System”, IEEE European Test Workshop (ETW), Cascais, Portugal (2000)
- P. Bukovjan : “Recherche de compromis coût/qualité dans un processus de synthèse en vue de la testabilité”, 博士论文, 答辩 2000-9-28, 责任导师 Marzouki, Meryem, 助理责任导师 BRZOBOHATY J. (2000)
1999
- P. Bukovjan, M. Marzouki, W. Maroufi : “Design for Testability Reuse in Synthesis for Testability”, XII Symposium on Integrated Circuits and Systems Design (SBCCI'99), Natal, RN, Brazil, pp. 206-209, (IEEE) (1999)
- P. Bukovjan, M. Marzouki, W. Maroufi : “Testability Analysis and Cost/Quality Trade-off in Synthesis for Testability”, 4^th IEEE European Test Workshop (ETW'99), Constance, Germany (1999)
- P. Bukovjan, M. Marzouki, W. Maroufi : “Testability Analysis in High-Level Synthesis”, 10^th European Workshop on Dependable Computing (EWDC), Vienna, Austria (1999)
1998
- P. Bukovjan, M. Marzouki, W. Maroufi : “Allocation for Testability in High-Level Synthesis Process”, 5^th Electronic Devices and Systems Conference, Brno, Czech Republic (1998)
- P. Bukovjan, M. Marzouki, W. Maroufi : “Cost/Quality Trade-off in High-Level Synthesis for Testability”, 2^nd International Workshop on Design and Diagnostics of Electronic Circuits and Systems, Szczyrk, Poland (1998)