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JAVID Farakh

Doutor em PhD
Equipe : CIAN
Data de partida : 04/10/2013
http://www-soc.lip6.fr/users/farakh.javid/
Direção de pesquisa : Habib MEHREZ
Co-supervisão£o : ISKANDER Ramy

Synthèse structurée des circuits analogiques intégrés capitalisant la connaissance du concepteur : vers une perspective industrielle

Driven by the rapid growth of the consumer electronics market, the need to reduce the design time for mixed-signal SoCs has never been so crucial. In that context, analog design, by its nature, is still mostly done by hand, thus remains time-consuming and involves weak design reuse, that is not compatible with the competition between ICs design companies. To tackle this issue, academic research led to the well-known simulation-based and knowledge-based analog synthesis systems. Based on these approaches, startups emerged to provide design companies and EDA vendors with synthesis tools. However, the use of analog synthesis tools in the industry is still limited. This is mainly due to their incompatibility with the full custom analog design task. Thus, a more promising approach lies in design assistance methodologies which take into account the designer knowledge, what is more likely to gain analog ICs designers trust. Moreover, leveraging the designer knowledge is a way to reduce the large design space associated with analog circuits design, what highlights the interest to capitalize the designer knowledge into a database. In that sense, the literature reports approaches that allow to express the designer expertise in the form of design equations, rules or programs. The main benefits of such approaches are the design freedom offered to the designer and the ability to store his knowledge for reuse. But their defects are the relative high set up time and complexity for the circuit design procedure capture, moreover the simplified device models used in the circuit design procedure do not match with the standard models used for verification. In this thesis, we present a new design methodology that tackles above issues to speed up analog circuits design. The methodology takes the advantages of both simulation-based and knowledge-based techniques to ensure the consistency and accuracy of the design, and it leverages a new knowledge formalization to provide more design insight and enable design reuse.
Defesas : 04/10/2013 - 15h30 - TOUR 55/65 Salle211
Membros da banca :
M. Maher KAYAL, EPFL, Suisse [Rapporteur]
M. Robert SOBOT, Université de Western, Canada [Rapporteur]
M. Andreas KAISER, IEMN, France
Mme. Noëlle LEWIS, IMS, France
M. François DURBIN, CEA-DAM, France
M. Habib MEHREZ, LIP6
M. Ramy ISKANDER, LIP6
Mme. Marie-Minerve LOUËRAT, LIP6

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