- Research
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Projects CIAN
Team : CIAN
ARCHitectures based on unconventional accelerators for dependable/energY efficienT AI Systems
Project Leader : Haralampos stratigopoulos
12/01/2024
Systèmes Bio-inspirés distribués de confiance : bases théoriques et mise en œuvre matérielle
Project Leader : Haralampos Stratigopoulos
10/01/2023
Trusted SMEs for Sustainable Growth of Europeans Economical Backbone to Strengthen the Digital Sovereignty
Project Leader : Haralampos Stratigopoulos
10/01/2023
A network of excellence for distributed, trustworthy, efficient and scalable AI at the Edge
Project Leader : Haralampos Stratigopoulos
09/01/2023
Compréhension et atténuation d’erreur dans les implémentations analogiques de réseaux de neurones sur silicium
Project Leader : Haralampos Stratigopoulos
10/01/2022
Récupération d'énergie mécanique proche des limites physiques par synthèse adiabatique de la dynamique électromécanique
C23/0800
Project Leader : Dimitri Galayko
10/01/2022
Architectures matérielles fiables pour l'Intelligence Artificielle de confiance
C22/0009
Project Leader : Haralampos Stratigopoulos
01/25/2022
CORIOLIS - Platform for physical synthesis of integrated circuits
Coriolis is an experimental integrated platform for the research, development and evaluation of new back-end VLSI design flows. Interconnect scaling to nanometer processes presents many difficult challenges to CAD flows. Currently academic research on back-end tend to address only specific algorithmic issues separately, although one key issue to address is the cooperation of multiple algorithmic tools. CORIOLIS, our platform, is based on an integrated C++ database around which all tools consistently interact and collaborate. This platform currently includes a timing-driven global place and route flow.
Project Leader : Jean-Paul CHAPUT
01/01/2004
CAIRO - Analog IP Design
Our purpose is to provide a language for designing generators of analog functions, that can be easily ported to new set of specfications and new technologogy processes. We are currently developing such a language that is called CAIRO+
The CAIRO+ language supports the four steps of a design flow based on net-list and layout templates. This language is aimed to help the designer to capture his knowledge, thus creating a library of layout-aware analog functions. It is based on C++ language. The design flow relevant to CAIRO+ is the following :
->net-list and layout template capture, ->design space exploration (managing electrical constraints) ->shape function computation (managing geometrical constraints) ->layout generation (place and route) CAIRO+ allows creating complex hierarchical analog function generators by using existing generators of simpler functions. It is an answer to the problem of Analog and Mixed IPs.
As a demonstration of the CAIRO+'s capabilities, we are developping Analog to Digital converters, specially Sigma Delta.
Project Leader : Marie-Minerve LOUËRAT
01/01/2004