Équipes actuelles : | ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL |
Ancienne équipe : | ACASA |
Publications ALSOC | 2023 | 2024 | Total |
---|---|---|---|
Livres | 0 | 0 | 0 |
Éditions de livres | 0 | 0 | 0 |
Articles de revues | 6 | 0 | 6 |
Chapitres de livres | 0 | 0 | 0 |
Conférences | 9 | 2 | 11 |
Habilitations | 0 | 0 | 0 |
Thèses | 3 | 0 | 3 |
- A. Drebes, K. Heydemann, N. Drach, A. Pop, A. Cohen : “Topology-Aware and Dependence-Aware Scheduling and Memory Allocation for Task-Parallel Languages”, ACM Transactions on Architecture and Code Optimization, vol. 11 (3), pp. 30, (Association for Computing Machinery) [Drebes 2014b]
- B. Dupont De Dinechin, A. Munier‑Kordon : “Converging to periodic schedules for cyclic scheduling problems with resources and deadlines”, Computers and Operations Research, vol. 51, pp. 227-236, (Elsevier) [Dupont De Dinechin 2014]
- S. Foroutan, A. Sheibanyrad, F. Pétrot : “Assignment of Vertical Links to Routers in Vertically-Partially-Connected 3D-NoCs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33 (8), pp. 1208-1218, (IEEE) [Foroutan 2014]
- Th. Hujsa, J.‑M. Delosme, A. Munier‑Kordon : “Polynomial Sufficient Conditions of Well-Behavedness and Home Markings in Subclasses of Weighted Petri Nets”, ACM Transactions on Embedded Computing Systems (TECS), vol. 13 (4), pp. 141:1-141:25, (ACM) [Hujsa 2014b]
- N. Moro, K. Heydemann, E. Encrenaz, B. Robisson : “Formal verification of a software countermeasure against instruction skip attacks”, Journal of Cryptographic Engineering, vol. 4 (3), pp. 145-156, (Springer) [Moro 2014c]
- A. Munier‑Kordon, D. Rebaine : “The coupled unit-time operations problem on identical parallel machines with respect to the makespan”, Operations Research Letters, vol. 42 (1), pp. 21-26, (Elsevier) [Munier-Kordon 2014]
- Zh. Zhang, D. Refauvelet, A. Greiner, M. Benabdenbi, F. Pêcheux : “On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22 (6), pp. 1364-1376, (IEEE) [Zhang 2014]