Подразделения :
ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL
LIP6
- N. Abdallah, P. Bazargan Sabet : “Modeling the Effects of Input Slew Rate and Temporal Proximity of Input Transitions in Event-Driven Simulation”, SSST IEEE Southeastern Symposium on System Theory, Cookeville, Tenessess, United States, pp. 185-189, (IEEE) [Abdallah 2006]
- Ch. Alexandre, M. Sroka, H. Clément, Ch. Masson : “Zephyr: a Static Timing Analyzer integrated in a trans-hierarchical refinement design flow”, PATMOS Power and Timing Modeling Optimization and Simulation, vol. 4148, Lecture Notes in Computer Science, Montpellier, France, pp. 319-328, (Springer) [Alexandre 2006]
- N. Beilleau, A. Kammoun, H. Aboushady : “Systematic Design Method for LC Bandpass Sigma-Delta Modulators with Feedback FIRDACs”, ISCAS IEEE International Symposium on Circuits and Systems, Kos, Greece, pp. 1896-1899, (IEEE) [Beilleau 2006]
- S. Belloeil, J.‑P. Chaput, R. Chotin‑Avot, Ch. Masson, H. Mehrez : “Stratus : Un environnement de développement de circuits”, JP CNFM Journées pédagogiques du CNFM, Saint-Malo, France, pp. 57-61 [Belloeil 2006]
- J. Bonan, Ch. Hagleitner, H. Aboushady : “Low-Power Cell-Level ADC for a MEMS-Based Parallel Scanning-Probe Storage Device”, ESSCIRC European Solid-State Circuits Conference, Montreux, Switzerland, pp. 239-242, (IEEE) [Bonan 2006]
- L. De Lamarre, M.‑M. Louërat, A. Kaiser : “Optimisation des éléments passifs d'un convertisseur sigma-delta temps continu”, TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Strasbourg, France, pp. 101-104 [De Lamarre 2006a]
- L. De Lamarre, M.‑M. Louërat, A. Kaiser : “Optimizing Resistances and Capacitances of a Continuous-Time Sigma-Delta Modulator”, ICECS IEEE International Conference on Electronics Circuits and Systems, Nice, France, pp. 419-422, (IEEE) [De Lamarre 2006b]
- D. Galayko, R. Iskander, M.‑M. Louërat, A. Greiner : “Réutilisation et migration d'amplificateurs avec CAIRO+”, JP CNFM Journées pédagogiques du CNFM, Saint Malo, France, pp. 35-39 [Galayko 2006b]
- A. Greiner, F. Pétrot, M. Carrier, M. Benabdenbi, R. Chotin‑Avot, R. Labayrade : “Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chip”, IV 2006 - IEEE Intelligent Vehicles Symposium, Tokyo, Japan, pp. 370-376, (IEEE) [Greiner 2006a]
- A. Greiner, F. Pétrot, M. Carrier, M. Benabdenbi, R. Chotin‑Avot, R. Labayrade : “MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation”, 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'06), Montpellier, France, pp. 24-30, (Université Montpellier II) [Greiner 2006b]
- R. Iskander, M.‑M. Louërat, A. Kaiser : “Dimensionnement automatique d'un circuit analogique à l'aide des transistors de référence”, TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Strasbourg, France, pp. 89-92 [Iskander 2006a]
- R. Iskander, M.‑M. Rosset‑Louërat, A. Kaiser : “Hierarchical Graph-Based Sizing for Analog Cells Through Reference Transistors”, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics Winner of the Bronze Leaf Certificate, Otranto, Italy, pp. 321-324, (IEEE) [Iskander 2006b]
- R. Iskander, P. Nguyen‑Tuong, L. De Lamarre, V. Bourguet, M.‑M. Louërat, A. Greiner : “Automated Hierarchical Knowledge-Based Synthesis for Analog Cells using CAIRO+”, Design Automation and Test in Europe Conference (DATE'2006), Munich, Germany [Iskander 2006c]
- A. Kammoun, N. Beilleau, H. Aboushady : “Undersampled LC bandpass Sigma-Delta modulators with Feedback FIRDACs”, ISCAS IEEE International Symposium on Circuits and Systems, Kos, Greece, pp. 4427-4430, (IEEE) [Kammoun 2006]
- O. Marchetti, A. Munier‑Kordon : “A polynomial algorithm for a bi-criteria cyclic scheduling problem.”, PlanSIG UK PLANNING AND SCHEDULING Special Interest Group, Nottingham, United Kingdom, pp. 88-96 [Marchetti 2006a]
- O. Marchetti, A. Munier‑Kordon : “Complexity results for bi-criteria cyclic scheduling problems”, RenPar Rencontres Francophones du Parallélisme, Perpignan, France, pp. 17-24 [Marchetti 2006b]
- Z. Marrakchi, H. Mrabet, H. Mehrez : “A new Multilevel Hierarchical MFPGA and its suitable configuration tools”, ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Karlsruhe, Germany, pp. 263-268, (IEEE) [Marrakchi 2006a]
- Z. Marrakchi, H. Mrabet, H. Mehrez : “Configuration tools for a new multilevel hierarchical FPGA”, FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, United States, pp. 229-229, (ACM) [Marrakchi 2006b]
- Z. Marrakchi, H. Mrabet, H. Mehrez : “Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent Parameter”, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto, Italy, pp. 85-88, (IEEE) [Marrakchi 2006c]
- Z. Marrakchi, H. Mrabet, H. Mehrez : “Performances comparison between Multilevel hierarchical and Mesh FPGA”, DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Tunis, Tunisia, pp. 166-171, (IEEE) [Marrakchi 2006d]
- H. Mrabet, Z. Marrakchi, H. Mehrez, A. Tissot : “Implementation of Scalable Embedded FPGA for SOC”, DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Tunis, Tunisia, pp. 74-77, (IEEE) [Mrabet 2006a]
- H. Mrabet, Z. Marrakchi, P. Souillot, H. Mehrez : “A multilevel hierarchical interconnection structure for FPGA”, FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, United States, pp. 225-225, (ACM) [Mrabet 2006b]
- H. Mrabet, Z. Marrakchi, P. Souillot, H. Mehrez : “Performances Improvement of FPGA using Novel Multilevel Hierarchical Interconnection Structure”, ICCAD IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, United States, pp. 675-679, (IEEE) [Mrabet 2006c]
- H. Mrabet, Z. Marrakchi, P. Souillot, H. Mehrez, A. Tissot : “Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure”, ReCoSoC 2006 - 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Montpellier, France, pp. 117-123, (Univ. Montpellier II) [Mrabet 2006d]
- M. Palus, F. Anceau : “JMQ, un processeur Java de hautes performances”, SympA Symposium en Architecture de Machines, Perpignan, France, pp. 154-165 [Palus 2006]