CIAN - Artigos de Conferencia

Pesquisa
Publicações
Research reports

Current teams : ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL

Publicações CIAN	2021	2022	2023	2024	2025	Total
Livros	0	0	0	0	0	0
Livros Editados	0	0	0	0	0	0
Jornais	8	9	6	3	1	27
Capítulos de livros	0	0	1	0	0	1
Artigos de Conferencia	15	15	6	10	10	56
Habilitações (Livre Docência)	0	0	0	0	0	0
Teses	4	0	2	1	0	7

LIP6

A. Abril Garcia, H. Mehrez, F. Pétrot, J. Gobert, C. Miro : “A High Level SoC Energy Analysis Method with Good Accuracy Using Cycle Accurate Simulation”, IEEE Symposium on low power and high-speed chips (COOL Chips VIII), Yokohama, Japan, pp. 195, (IEEE) [Abril Garcia 2005a]
A. Abril Garcia, H. Mehrez, F. Pétrot, J. Gobert, C. Miro : “Energy Estimation and Optimisation of Embedded Systems using Cycle Accurate Simulation”, FTFC 2005 - 5èmes Journées d'études Faible Tension Faible Consommation, Paris, France, pp. 29-32 [Abril Garcia 2005b]
A. Abril Garcia, H. Mehrez, F. Pétrot, J. Gobert, C. Miro : “Energy estimation and optimization in architectural descriptions of complex embedded systems”, Microtechnologies for the New Millennium 2005 : VLSI Circuits and Systems, vol. 5837, SPIE Proceedings, Sevilla, Spain, pp. 456-466, (SPIE) [Abril Garcia 2005c]
Ch. Alexandre, H. Clément, J.‑P. Chaput, M. Sroka, Ch. Masson, R. Escassut : “TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform”, DATE 2005 - Design Automation and Test in Europe Conference, vol. 2, Munich, Germany, pp. 920-921, (IEEE) [Alexandre 2005]
N. Beilleau, H. Aboushady, M.‑M. Rosset‑Louërat : “Using Finite Impulse Response Feedback DACs to design Sigma-Delta modulators based on LC filters”, MWSCAS 2005 - 48^th Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, United States, pp. 696-699, (IEEE) [Beilleau 2005]
S. Belloeil, H. Mehrez : “Optimisation de chemins de données par l'utilisation de l'arithmétique redondante”, JNRDM 2005 - 8èmes Journées Nationales du Réseau Doctoral en Microélectronique, Paris, France, pp. 268-270 [Belloeil 2005]
L. De Lamarre, M.‑M. Louërat, A. Kaiser : “Un convertisseur flash 4 bits à base de transistors MOS consommant 3,8mW à 300MHz”, TAISA 2005 - 6ème Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Marseille, France, pp. 57-60 [De Lamarre 2005a]
L. De Lamarre, M.‑M. Rosset‑Louërat, A. Kaiser : “A simple 3.8mW, 300 MHz, 4-bit flash analog-to-digital converter”, Microtechnologies for the New Millennium 2005 VLSI Circuits and Systems II, vol. 5837, SPIE Proceedings, Sevilla, Spain, pp. 825-832, (The International Society for Optical Engineering) [De Lamarre 2005b]
D. Dupuis : “Etude comparative de deux algorithmes de placement de systèmes intégrés sur puce”, JNRDM 2005 - Journées Nationales du Réseau Doctoral en Microélectronique, Paris, France, pp. 55-57 [Dupuis 2005]
R. Iskander, L. De Lamarre, P. Nguyen‑Tuong, M.‑M. Louërat, A. Kaiser : “Synthèse d'un IP amplificateur analogique CMOS avec CAIRO+”, TAISA 2005 - 6ème Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Marseille, France, pp. 69-72 [Iskander 2005a]
R. Iskander, M.‑M. Rosset‑Louërat, A. Kaiser : “Automatic Biasing Point Extraction and Design Plan Generation for Analog IPs”, MWSCAS 2005 - 48^th Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, United States, pp. 907-910, (IEEE) [Iskander 2005b]
D. Khalil, M. Dessouky, V. Bourguet, M.‑M. Rosset‑Louërat, A. Cathelin, H. Ragai : “Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays”, ISQED 2005 - 6^th International Symposium on Quality of Electronic Design, San Jose, California, United States, pp. 143-147, (IEEE) [Khalil 2005]
A. Latiri, H. Aboushady, N. Beilleau : “Design of Continuous-Time Sigma-Delta Modulators with Sine-Shaped Feedback DACs”, ISCAS 2005 - IEEE International Symposium on Circuits and Systems, Kobe, Japan, pp. 3672-3675, (IEEE) [Latiri 2005]
Z. Marrakchi, H. Mrabet, H. Mehrez : “Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation”, ReConFig 2005 - International Conference on Reconfigurable Computing and FPGAs, Puebla City, Mexico, pp. 21-25, (IEEE Computer Society) [Marrakchi 2005a]
Z. Marrakchi, H. Mrabet, H. Mehrez : “Hierarchical FPGA clustering to improve routability”, PRIME 2005 - IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, vol. 1, Lausanne, Switzerland, pp. 165-168, (IEEE) [Marrakchi 2005b]
H. Mrabet, Z. Marrakchi, H. Mehrez, A. Tissot : “Implementation of Scalable Embedded FPGA for SOC”, ReCoSoC 2005 - 1^st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Montpellier, France, pp. 74-77 [Mrabet 2005]
P. Renault, P. Bazargan Sabet : “Capturing RC-Interconnect Effect in Crosstalk Analysis”, MIXDES 2005 - 12^th International conference on Mixed Design of Integrated Circuits and Systems, Krakow, Poland, pp. 309-314 [Renault 2005]
M. Sroka : “Zephyr : Un outil d'analyse de timing pour placement-routage timing-driven de systèmes intégrés sur puce”, JNRDM 2005 - 8èmes Journées Nationales du Réseau Doctoral en Microélectronique, Paris, France [Sroka 2005]