| Équipes actuelles : | ACASA ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL |
| Ancienne équipe : | Phare |
| Publications ALSOC | 2017 | 2018 | 2019 | 2020 | 2021 | 2022 | 2023 | Total |
|---|---|---|---|---|---|---|---|---|
| Livres | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Éditions de livres | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 2 |
| Articles de revues | 4 | 3 | 3 | 5 | 3 | 3 | 6 | 27 |
| Chapitres de livres | 0 | 2 | 1 | 0 | 0 | 0 | 0 | 3 |
| Conférences | 11 | 17 | 17 | 13 | 15 | 11 | 8 | 92 |
| Habilitations | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| Thèses | 2 | 0 | 2 | 3 | 2 | 2 | 3 | 14 |
- Th. Barry, D. Couroussé, B. Robisson, K. Heydemann : “Automated Combination of Tolerance and Control Flow Integrity Countermeasures against Multiple Fault Attacks”, European LLVM Developers Meeting, Saarbrücken, Germany [Barry 2017]
- H. Bel Hadj Amor, A. Sheibanyrad, F. Pétrot : “A Distributed NUCA Architecture Using an Efficient NoC Multicasting Support”, Euromicro Conference on Digital System Design (DSD 2017), Vienne, Austria, pp. 184-191, (IEEE) [Bel Hadj Amor 2017a]
- H. Bel Hadj Amor, A. Sheibanyrad, F. Pétrot : “A Meta-Routing Method to Create Multiple Virtual Logical Networks on a Single Hardware NoC”, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, pp. 200-205, (IEEE) [Bel Hadj Amor 2017b]
- N. Belleville, Th. Barry, A. Seriai, D. Couroussé, K. Heydemann, B. Robisson, H.‑P. Charles : “The Multiple Ways to Automate the Application of Software Countermeasures against Physical Attacks : Pitfalls and Guidelines”, Cyber-Physical Security Education Workshop, Paris, France [Belleville 2017]
- I. Ben El Ouahma, Quentin L. Meunier, K. Heydemann, E. Encrenaz : “Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes”, Security Proofs for Embedded Systems, Taipei, China [Ben El Ouahma 2017]
- L. Cabaret, L. Lacassagne, D. Etiemble : “Distanceless Label Propagation: an Efficient Direct Connected Component Labeling Algorithm for GPUs”, IPTA2017 - International Conference on Image Processing Theory, Tools and Applications, Montreal, Canada [Cabaret 2017]
- H. Deroui, K. Desnos, J.‑F. Nezan, A. Munier‑Kordon : “Relaxed Subgraph Execution Model for the Throughput Evaluation of IBSDF Graphs”, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), SAMOS, Greece [Deroui 2017a]
- H. Deroui, K. Desnos, J.‑F. Nezan, A. Munier‑Kordon : “Throughput Evaluation of DSP Applications based on Hierarchical Dataflow Models”, International Symposium on Circuits and Systems (ISCAS), Baltimore, United States [Deroui 2017b]
- D. Genius, L. Apvrille : “System-Level Design for Communication-Centric Task Farm Applications”, 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, Madrid, Spain [Genius 2017a]
- D. Genius, L. Li, L. Apvrille : “Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design”, Modeling Languages, Tools and Architectures, Methodologies, Processes and Platforms, Applications and Software Development (MODELSWARD), Porto, Portugal [Genius 2017b]
- H. Liu, Quentin L. Meunier, A. Greiner : “Decoupling Translation Lookaside Buffer Coherence from Cache Coherence”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), Bochum, Germany, pp. 92-97, (IEEE) [Liu 2017]