ALSOC - Conférences

Équipes actuelles :

ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL

Publications ALSOC	2023	2024	Total
Livres	0	0	0
Éditions de livres	0	0	0
Articles de revues	6	1	7
Chapitres de livres	0	0	0
Conférences	9	7	16
Habilitations	0	0	0
Soutenances de thèse	3	2	5

LIP6

M. Agoyan, P. Bazargan Sabet, K. Bekkou, B. Sylvain, S. Le Henaff, E. Lepavec, M. Nguyen, G. Phan, B. Robisson, P. Soquet, F. Wajsbürt : “Smart On Smart”, Colloque « Systèmes embarqués, sécurité et sûreté de fonctionnement », Toulouse, France [Agoyan 2010b]
S. Baarir, C. Braunstein, E. Encrenaz, J.‑M. Ilié, T. Li, I. Mounier, D. Poitrenaud, S. Younes : “Quantifying Robustness by Symbolic Model checking”, 1^st Hardware Verification Workshop (CAV workshop), Edinburgh, United Kingdom, pp. 1-12 [Baarir 2010a]
A. Bara, P. Bazargan Sabet, R. Chevallier, E. Encrenaz, D. Le Dû, P. Renault : “Formal Verification of Timed VHDL Programs”, Forum on Specification & Design Languages, FDL 2010, Southampton, United Kingdom, pp. 80-85, (IET) [Bara 2010]
M. Barnasconi, K. Einwich, Ch. Grimm, F. Pêcheux : “Tutorial f1 : Application of the systemc-ams standard”, DATE 2010 - IEEE International Conference on Design, Automation and Test in Europe, Dresden, Germany [Barnasconi 2010]
M. Benazouz, O. Marchetti, A. Munier‑Kordon, P. Urard : “A new Approach for Minimizing Buffer Capacities with Throughput Constraint for Embedded System Design.”, AICCSA IEEE/ACS International Conference on Computer Systems and Applications, Hammamet, Tunisia, pp. 1-8, (IEEE) [Benazouz 2010a]
M. Benazouz, O. Marchetti, A. Munier‑Kordon, Th. Michel : “A New Method for Minimizing Buffer Sizes for Cyclo-Static Dataflow Graphs.”, ESTIMedia 2010 - 8^th IEEE International Workshop on Embedded Systems for Real-Time Multimedia, Scottsdale, Arizona, United States, pp. 11-20, (IEEE) [Benazouz 2010b]
P. Berthomé, K. Heydemann, X. Kauffmann‑Tourkestansky, J.‑F. Lalande : “Attack model for verification of interval security properties for smart card C codes”, PLAS '10 - 5^th ACM SIGPLAN Workshop on Programming Languages and Analysis for Security, Toronto, Canada, pp. 2:1-2:12, (ACM) [Berthomé 2010]
H. Cassé, K. Heydemann, H. Ozaktas, J. Ponroy, Ch. Rochange, O. Zendra : “A framework to experiment optimizations for real-time and embedded software”, International Conference on Embedded Real Time Software and Systems (ERTS2), Toulouse, France [Cassé 2010]
E. Faure, G. Marchesan Almeida, M. Benabdenbi, P. Benoit, F. Clermidy, F. Pêcheux, G. Sassatelli, L. Torres : “An In-Memory Monitoring Database For Self Adaptive MP²SoCs”, IEEE International Conference on Design and Architectures for Signal and Image Processing, Edimbourg, United Kingdom, pp. 97-104 [Faure 2010a]
E. Faure, M. Benabdenbi, F. Pêcheux : “Distributed online software monitoring of manycore architectures”, 16^th IEEE International On-Line Testing Symposium, Corfou Island, Greece, pp. 56-61, (IEEE) [Faure 2010b]
A. Habib, F. Pêcheux : “Modeling and simulation of a manycore pcr-ce lab-on-chip for dna sequencing using systemc/systemc-ams”, BMAS : 2010 IEEE International Behavioral Modeling and Simulation Conference, San Jose, CA, United States, pp. 63-68, (IEEE) [Habib 2010a]
A. Habib, F. Pêcheux, M.‑M. Louërat : “Systemc-ams modeling of a pcr-ce lab-on-chip for multithreaded dna analysis”, 22^nd International Conference on Microelectronics (ICM), Cairo, Egypt, pp. 483-486, (IEEE) [Habib 2010b]
A. Lévêque, F. Pêcheux, M.‑M. Louërat, H. Aboushady, M. Vasilevski : “SystemC-AMS Models for Low-Power Heterogeneous Designs: Application to a WSN for the Detection of Seismic Perturbations”, ARCS '10 - 23^th International Conference on Architecture of Computing Systems, Hannover, Germany, pp. 1-6 [Lévêque 2010]
A. Massouri, A. Lévêque, L. Clavier, M. Vasilevski, A. Kaiser, M.‑M. Louërat : “Baseband Fading Channel Simulator for Inter-Vehicle Communication using SystemC-AMS”, 2010 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2010), San Jose, CA, United States, pp. 36-41 [Massouri 2010]
M.‑H. Nguyen, B. Robisson, M. Agoyan, N. Drach : “Low-cost fault tolerance on the ALU in simple pipelined processors”, DDECS 2010 - 13^th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienne, Austria, pp. 28-31, (IEEE) [Nguyen 2010]
F. Pêcheux, A. Habib : “Towards high-level executable specifications of heterogeneous systems with systemc-ams : Application to a manycore pcr-ce lab on chip for dna sequencing.”, Forum on Specification and Design Languages, FDL 2010, Southampton, United Kingdom, pp. 1-6, (IEEE) [Pêcheux 2010a]
F. Pêcheux, Kh. Zine el Abidine, A. Greiner : “Early power estimation in heterogeneous designs using Soclib and Systemc-ams”, International Workshop on Power And Timing Modeling Optimization and Simulation, PATMOS, vol. 6448, Lecture Notes in Computer Science, Grenoble, France, pp. 252, (Springer) [Pêcheux 2010b]
F. Pêcheux, M. Madec, Ch. Lallement : “Is systemc-ams an appropriate promoter for the modeling and simulation of bio-compatible systems ?”, ISCAS : Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 2010. IEEE Computer Society., Paris, France, pp. 1791-1794, (IEEE) [Pêcheux 2010c]
P. Soquet, B. Robisson, M. Agoyan, G. Phan, P. Bazargan Sabet, F. Wajsbürt : “Strategy Of Security on Smart On Smart”, PACA Security Trends In embedded Security, Gardanne, France [Soquet 2010]
S. Taktak, E. Encrenaz, J.‑L. Desbarbieux : “A polynomial algorithm to prove deadlock-freeness of wormhole networks”, PDP EUROMICRO Conference on Parallel, Distributed and Network-based Computing IEEE Computer Society, Pisa, Italy, pp. 121-128, (IEEE) [Taktak 2010]
A. Vieira De Mello, I. Maïa Pessoa, A. Greiner, F. Pêcheux : “Parallel Simulation of SystemC TLM 2.0 Compliant MPSoC on SMP Workstations”, DATE 2010 - Design, Automation & Test in Europe Conference & Exhibition, Dresden, Germany, pp. 606-609 [Vieira De Mello 2010]
Zh. Zhang, A. Greiner, M. Benabdenbi : “Fully Distributed Initialization Procedure for a 2D-Mesh NoC, Including Off Line BIST and Partial Deactivation of Faulty Components”, The 16^th IEEE International On-Line Testing Symposium (IOLTS), Corfu, Greece, pp. 194-196 [Zhang 2010]