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equipos actuales : ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL

Publicaciones ALSOC	2021	2022	2023	2024	2025	Total
Libros	0	0	0	0	0	0
Libros editados	0	0	0	0	0	0
Artículos de revistas	4	4	7	1	1	17
Capítulos de libros	0	0	0	0	0	0
Documentos de conferencias	15	11	9	7	1	43
Habilitaciones	0	0	0	0	0	0
Tesis	2	2	3	2	0	9

LIP6

C. Braunstein, E. Encrenaz : “Using CTL formulae as component abstraction in a design and verification flow”, ACSD IEEE International Conference on Application of Concurrency to System Design, Bratislava, Slovakia, pp. 80-89, (IEEE) [Braunstein 2007b]
R. Buchmann, A. Greiner : “A Fully Static Scheduling Approach for Fast Cycle Accurate SystemC Simulation of MPSoCs”, ICM International Conference on Microelectronics, Cairo, Egypt, pp. 105-108, (IEEE) [Buchmann 2007]
E. Encrenaz, A. Finkel : “Automatic Verification of Counter Systems with Ranking Functions”, INFINITY International Symposium on Infinite-Space Systems, Porto, Portugal [Encrenaz 2007]
Th. Finateu, I. Miro Panades, F. Boissières, J.‑B. Bègueret, Y. Deval, D. Belot, F. Badets : “A 500-Mhz Sigma-Delta Phase Interpolation Direct Digital Synthesizer”, A-SSCC IEEE Asian Solid-State Circuits Conference, Jeju, Korea, Republic of, pp. 452-455, (IEEE) [Finateu 2007]
D. Genius, E. Faure, N. Pouillon : “Deploying a Telecommunication on Multiprocessor Systems-on-Chip”, International Conference on Design and Architectures for Signal and Image Processing, Grenoble, France, pp. 1-8 [Genius 2007]
I. Miro‑Panades, A. Greiner : “Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures”, NoC ACM/IEEE International Symposium on Networks-on-Chip, Princeton, NJ, United States, pp. 83-94, (IEEE), (ISBN: 0-7695-2773-6) [Miro-Panades 2007]
K. Paul, J. Porquet : “Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration”, DSD EUROMICRO Conference on Digital System Design, Lübeck, Germany, pp. 317-324, (IEEE) [Paul 2007]
A. Sheibanyrad, A. Greiner : “Hybrid-Timing FIFOs to use on Networks-on-Chip in GALS Architectures”, ESA International Conference on Embedded Systems and Applications, Las Vegas, Nevada, United States, pp. 27-33, (CSREA Press) [Sheibanyrad 2007a]
A. Sheibanyrad, I. Miro Panades, A. Greiner : “Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture”, DATE Design Automation and Test in Europe Conference 2007, Nice, France, pp. 1090-1095, (IEEE) [Sheibanyrad 2007b]
M. Tuna, M. Benabdenbi, A. Greiner : “At-Speed Testing of Core-Based System-On-Chip Using an Embedded Micro-Tester”, VTS IEEE VLSI Test Symposium, Berkeley, California, United States, pp. 447-454, (IEEE) [Tuna 2007a]
M. Tuna, O. Garcia, M. Benabdenbi : “Software-Based Self-Test Strategies for Memory Caches of RISC Processor Cores”, LATW IEEE Latin-American Test Workshop, Cuzco, Peru, pp. 124-130 [Tuna 2007b]
M. Vasilevski, F. Pêcheux, H. Aboushady, L. De Lamarre : “Modeling heterogeneous systems using SystemC-AMS case study: A Wireless Sensor Network Node”, Behavioral Modeling and Simulation Workshop, 2007. BMAS 2007. IEEE International, San Jose, CA, United States, pp. 11-16, (IEEE) [Vasilevski 2007a]