ALSOC - Artigos de Conferencia

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Publicações
Research reports

Current teams : ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL

Publicações ALSOC	2021	2022	2023	2024	2025	Total
Livros	0	0	0	0	0	0
Livros Editados	0	0	0	0	0	0
Jornais	4	4	7	1	1	17
Capítulos de livros	0	0	0	0	0	0
Artigos de Conferencia	15	11	9	7	1	43
Habilitações (Livre Docência)	0	0	0	0	0	0
Teses	2	2	3	2	0	9

LIP6

C. Braunstein, E. Encrenaz : “A Further Step in the Incremental Design Process: Incorporation of an Increment Specification”, LPAR IEEE International Conference on Logic for Programming Artificial Intelligence and Reasoning, Phnom Penh, Cambodia, pp. short paper [Braunstein 2006a]
C. Braunstein, E. Encrenaz : “Formalizing the incremental design and verification process of a pipelined protocol converter”, RSP International Workshop on Rapid System Prototyping, Chania, Crete, Greece, pp. 103-109, (IEEE) [Braunstein 2006b]
R. Buchmann, A. Greiner : “Automatic Translation of SystemC Simulation Model From VHDL RTL Model : a Semantic Approach”, DATE Design Automation and Test in Europe Conference, Munich, Germany [Buchmann 2006]
M. Carrier, A. Greiner : “Détection d'obstacles en contexte routier par stéréo vision sur un système intégré sur puce”, JNRDM Journées Nationales du Réseau Doctoral en Microélectronique, Rennes, France, pp. 243-245 [Carrier 2006]
A. Coveliers, K. Heydemann, N. Drach : “Sensibilité aux jeux de données de la compilation itérative”, SympA Symposium en Architecture de Machines, Perpignan, France, pp. 35-46 [Coveliers 2006]
E. Encrenaz, L. Fribourg : “Time separation of events, an inverse method”, LIX Colloquium on emerging Trends in Concurrency Theory, Palaiseau, France [Encrenaz 2006]
E. Faure, A. Greiner, D. Genius : “A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications”, ReCoSoC Reconfigurable Communication-centric SoCs, Montpellier, France, pp. 237-242 [Faure 2006]
D. Galayko, R. Iskander, M.‑M. Louërat, A. Greiner : “Réutilisation et migration d'amplificateurs avec CAIRO+”, JP CNFM Journées pédagogiques du CNFM, Saint Malo, France, pp. 35-39 [Galayko 2006b]
A. Greiner, F. Pétrot, M. Carrier, M. Benabdenbi, R. Chotin‑Avot, R. Labayrade : “Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chip”, IV 2006 - IEEE Intelligent Vehicles Symposium, Tokyo, Japan, pp. 370-376, (IEEE) [Greiner 2006a]
A. Greiner, F. Pétrot, M. Carrier, M. Benabdenbi, R. Chotin‑Avot, R. Labayrade : “MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation”, 2^nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'06), Montpellier, France, pp. 24-30, (Université Montpellier II) [Greiner 2006b]
R. Iskander, P. Nguyen‑Tuong, L. De Lamarre, V. Bourguet, M.‑M. Louërat, A. Greiner : “Automated Hierarchical Knowledge-Based Synthesis for Analog Cells using CAIRO+”, Design Automation and Test in Europe Conference (DATE'2006), Munich, Germany [Iskander 2006c]
I. Miro Panades, A. Greiner, A. Sheibanyrad : “A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach”, NanoNet International Conference on Nano-Networks, Lausanne, Switzerland, pp. 1-5, (IEEE) [Miro Panades 2006a]
I. Miro Panades, A. Greiner, A. Sheibanyrad : “Micro-réseau sur puce compatible avec l'approche GALS”, Journées Nationales du Réseau Doctoral de Micro-électronique, Rennes, France, pp. 1-5 [Miro Panades 2006b]
F. Pétrot, A. Greiner, P. Gomez : “On cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures”, 9^th EUROMICRO Conference on Digital System Design (DSD'06), Dubrovnik, Croatia, pp. 53-60, (IEEE Computer Society) [Pétrot 2006]
A. Sheibanyrad, A. Greiner : “Two Efficient Synchronous ⇔ Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures”, International Workshop on Power And Timing Modeling Optimization and Simulation, vol. 4148, Lecture Notes in Computer Science, Montpellier, France, pp. 192-202, (Springer) [Sheibanyrad 2006]
S. Taktak, E. Encrenaz, J.‑L. Desbarbieux : “A Tool for Automatic Detection of Deadlock in Wormhole Networks on Chip”, HLDVT IEEE International High Level Design Validation and Test Workshop, Monterey, California, United States, pp. 203-210, (IEEE) [Taktak 2006]
M. Tuna, M. Benabdenbi : “Software-Based Self-Test of Register Files in RISC Processor Cores using March Algorithms”, LATW IEEE Latin-American Test Workshop digest of papers, Buenos Aires, Argentina, pp. 67-72 [Tuna 2006a]
M. Tuna, M. Benabdenbi, A. Greiner : “STESOC: A Software-Based Test-Access-Mechanism Controller”, ETS IEEE European Test Symposium, Southampton, United Kingdom, pp. 91-96 [Tuna 2006b]
M. Tuna, M. Benabdenbi, A. Greiner : “T-Proc: An Embedded IEEE1500-Wrapped Cores Tester”, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto, Italy, pp. 493-496, (IEEE) [Tuna 2006c]
E. Viaud, F. Pêcheux : “A New Paradigm and Associated Tools for TLM/T Modeling of MPSoCs”, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto, Italy, pp. 217-220, (IEEE) [Viaud 2006a]
E. Viaud, F. Pêcheux, A. Greiner : “An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles”, DATE Design Automation and Test in Europe Conference, Munich, Germany, pp. 94-99, (IEEE) [Viaud 2006b]