LIP6 2004/006
- Thesis
Architectures matérielles pour l'arithmétique stochastique discrète - R. Chotin-Avot
- 168 pages - 06/06/2003- document en - http://www.lip6.fr/lip6/reports/2004/lip6.2004.006.pdf - 1,808 Ko
- Contact : Roselyne.Avot (at) nulllip6.fr
- Ancien Thème : ASIM
- Keywords : CESTAC method, stochastic arithmetic, floating-point arithmetic, accuracy estimation, accuracy control, system on chip, accelerator of calculation, adequacy algorithm VLSI architecture.
- Publisher : Francois.Dromard (at) nulllip6.fr
The use of floating point arithmetic in scientific computations is a source of problems of precision. Since all real numbers cannot represented in floating-point format, some will have to be approximated. The discrete stochastic arithmetic permits to control and estimate rounding errors. The software implementation of this arithmetic suffers from computation bottlenecks. The aim of this thesis is to propose a hardware architecture to reduce this cost. First we implemented in hardware the specific functionalities of discrete stochastic arithmetic which are the random rounding mode, the computation of the number of significant bits, the detection of informatical zeroes and the control of the operations of comparison. Second, since the discrete stochastic arithmetic is based on floating-point arithmetic, we developed a floating-point unit. The specific hardware, need for the control and the estimation of round-off errors propagation, was added. Thus a floating-point unit computing the operations of addition, subtraction, multiplication, division, comparison and conversions, with estimation and control of the round-off errors, was developed to the physical layout. Finally we integrated this unit in a system on chip to be able to use it by computing programs and to compare the performances with the software.