LIP6 2002/004
- Thesis
Analyse du Bruit dû aux couplages capacitifs dans les Circuits Intégrés numériques fortement Submicroniques - F. Ilponse
- 156 pages - 04/26/2002- document en - http://www.lip6.fr/lip6/reports/2002/lip6.2002.004.pdf - 1,174 Ko
- Contact : Fabrice.Ilponse (at) nulllip6.fr
- Ancien Thème : ASIM
- Keywords : Verification, Noise, Capacitive crosstalk, Submicron, Voltage peak, Timing, Data structure
- Publisher : Francois.Dromard (at) nulllip6.fr
This thesis aims at the full chip verification in the deep submicron technologies. The circuit descriptions are transistor netlists with ground and coupling capacitances. The studied phenomenon is the capacitive crosstalk. In this manuscript, we propose a method to compute the noise occurring on the circuit signals. This noise is the voltage peak due to the current injections from the neighbouring signals thru the coupling capacitances. A designer generally expects the higher noise value occurring on each signal and also the neighbour signals generating this noise. As the noise is linked to the circuit activity, two methods are exposed. They take into account the switching signals in the circuit to be closer to the circuit behaviour. The first method is a worst case and the second one includes the timing aspects of the circuit by selecting the signals using their instability gaps. Finally, an appropriate data structure to handle today huge chips is described. All the computations are done using this data structure. A prototype tool using all the concepts of this thesis, CRISE (Crosstalk RISk Evaluation), has been created. This tool demonstrates the data structure efficiency to handle multi-million transistor circuits, the worth of the signal discriminations and the noise computation model on the victim signals which appreciable accuracy compared electrical simulation tools. CRISE has successfully analysed a chip with more than one million transistors in an acceptable time.