LIP6 2000/019

• Thesis
  Un Réseau d'interconnexion pour systèmes intégrés
• P. Guerrier
• 150 pages - 05/31/2000- document en - http://www.lip6.fr/lip6/reports/2000/lip6.2000.019.ps.tar.gz - 1,028 Ko
• Contact : Pierre.Guerrier (at) nulllip6.fr
• Ancien Thème : ASIM
We present an interconnection network for heterogeneous multiprocessor integrated circuits, using techniques inspired by supercomputer networks. We show that this architecture relieves the constraints of the _shared central bus_ model, which becomes critical in deeply submicronic fabrication processes. We also show that the use of a network conflicts with bus-oriented legacy processors. In order to preserve existing assets, we present a method to offer point-to-point stream communications over our network. The cost and performance of our architecture are estimated on the basis of a tentative implementation.
• Keywords : VLSI, integrated circuits, systems-on-a-chip, multistage networks, packet switching, communication protocols, multiprocessors, parallel computing
• Publisher : Francois.Dromard (at) nulllip6.fr