Architecture d'un système hétérogène pour la reconnaissance de formes
- M. Aberbour
- 220 pages - 29/09/1999- document en - http://www.lip6.fr/lip6/reports/1999/lip6.1999.022.ps.tar.gz - 4,757 Ko
- Contato : Mourad.Aberbour (at) nulllip6.fr
- Ancien Thème : ASIM
- Palavras chaves : Harware/Software codesign, VLSI architectures, pattern recognition, image processing, artificial neural networks, Gabor wavelets, Algorithm/Architecture Adequation, module generator, cycle precise simulation
- Diretor de publicação : Francois.Dromard (at) nulllip6.fr
In recent years, biologically inspired computer vision has seen a growing research interest from the scientific community. However, the inherent processing involved in artificial vision systems implies intensive computations. Such systems need hardware acceleration, and miniaturization for real-time embedded applications. Fortunately, advances in integration technology allow the implementation of complex systems of tens of millions transistors on a single chip. The work achieved during this thesis concerns the algorithmic and architectural study of a real time pattern recognition system based on a modeling of biological vision. The system must satisfy many types of invariance of an objet in a complex scene such us orientation, scale, perspective, noise, occlusion, etc. We have used proven algorithms to propose a recognition method optimized for a VLSI integration. These algorithms are based on an analysis using Gabor wavelets, followed by extraction of pertinent characteristics with the saliency algorithms introduced by Clark, and finally we use an RBF artificial neural network trained with the DDA algorithm for learning and classification. The choice of these different algorithms and their refinement have been motivated by the VLSI integration of the system. The algorithms, as originally specified, cannot be readily integrated on a chip. It has been necessary to refine them to make their VLSI implementation possible. To achieve this algorithm/architecture adequacy operation, we have proposed a methodology satisfying the design constraints. The investigation of existing candidate architectures, for the hardware implementation of our system, led us to propose a heterogeneous hardware/software architecture. A general purpose RISC processor is tied to high performance modules, also called coprocessors, designed specifically to accelerate a given algorithm. The comparative study of alternative solutions has been made easier by the use of a cycle precise hardware/software simulator. The dedicated coprocessors are designed to offer the best performances while being parametrizable. To satisfy these constraints we used a VLSI design environment based on the module generator concept. This is of great value, since it allows the reuse of the coprocessors in diverse applications and their mapping on different target integration technologies.