LIP6 1999/018
- Thesis
Aide à la conception de systèmes testables - W. Maroufi
- 171 pages - 07/02/1999- document en - http://www.lip6.fr/lip6/reports/1999/lip6.1999.018.ps.gz - 589 Ko
- Contact : Walid.Maroufi (at) nulllip6.fr
- Ancien Thème : ASIM
- Keywords : Systems, boards, MCMs, testability
- Publisher : Francois.Dromard (at) nulllip6.fr
Despite the growing interest in integrated systems on a chip (SoCs), testability and maintainability of discrete electronic systems is still a critical issue in fields like avionics. However, industrial needs for tools dedicated to system design for testability are far from being satisfied. Such tools must meet different needs in order to follow all the steps of a system life cycle, from its design to its life time maintenance. Standardized test architectures exist for circuits (SCAN, BIST), for boards (IEEE-1149.1) as well for systems (IEEE-1149.5). Integrated systems are also taken into account in recent works, such as those of VSIA consortium and P1500 working group. These test techniques, protocols and architectures are the elements on which can be based global strategies for testability of electronic and micro-electronic systems. With the growing complexity of the systems, the designers have to take into account various constraints, and the choices they have to make become difficult. This is actually the context of this research work. A new method that helps the design of testable systems is proposed. It is meant to drive the designer in the inclusion of test functionalities in all the steps of the system development. This method has a twofold objective. It first enables to optimize the test development time by studying as soon as possible the system testability in the design process and by getting the designers and the test experts closer. The second objective is to develop a test architecture able to ensure an efficient and reliable further maintenance. The proposed method has been embedded in the STA tool that we have developed. It uses a bottom-up approach processing. Starting by the circuits, the boards or MCMs, and then the system testability. At each level, test strategies are proposed and decisions are made interactively between the user and the tool. A strategy for the evaluation of the boards, MCMs and eventually integrated systems testability, is also proposed and integrated in the method. Gateways to test structures generation tools, circuit level testability analysis, synthesis for testability or high level synthesis, makes the method modular.