LIP6 1998/006

• Thesis «Méthode de simulation logico-temporelle de circuits numériques complexes prenant en compte le front des signaux et les collisions dans le cadre de la simulation mixte analogique-numérique»
• N. Abdallah
• 135 pages - 02/01/1998 - document en - http://www.lip6.fr/lip6/reports/1998/lip6.1998.006.ps.gz 1,555 Ko
• Contact nizar (at) nullieee.org
• Ancien Thème : ASIM
This thesis addresses the problem of verifying a general circuit description, wherein, the input is a flat transistor and capacitance net-list, obtained from a layout extractor. A new simulation approach is proposed that redefines the concept of event within the event-driven simulation paradigm. It maximally utilizes the idiosyncrasy that, in most cases, the general shape of a digital MOS signal can be represented by a function with one temporal parameter. In this case, the temporal parameter represents the slope. Unlike conventional techniques, in our approach, an event occurs on a slope change rather than a voltage change, thereby, reducing the number of events during the simulation. High degree of accuracy is achieved by using deep submicron MOS I-V characteristics, by including slope effect, and by accounting for temporal proximity of multiple input transitions. Also, a prototype simulator has been implemented using the above technique. It performs simulation runs with an accuracy typically within 5% of the SPICE circuit simulator results, and yet is still more than three orders of magnitude faster.