1 PhD graduated 2010

1997-2012 Publications

• 2012
  • M. Rosière, J.‑L. Desbarbieux, N. Drach, F. Wajsbürt : “An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design”, DATE Design Automation and Test in Europe Conference, Dresden, Germany, pp. 1549-1554, (IEEE) (2012)
• 2011
  • M. Rosière, J.‑L. Desbarbieux, N. Drach, F. Wajsbürt : “MORPHEO: a high-performance processor generator for a FPGA implementation”, DASIP IEEE International Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, pp. 1-8, (IEEE) (2011)
• 2010
  • S. Taktak, E. Encrenaz, J.‑L. Desbarbieux : “A polynomial algorithm to prove deadlock-freeness of wormhole networks”, PDP EUROMICRO Conference on Parallel, Distributed and Network-based Computing IEEE Computer Society, Pisa, Italy, pp. 121-128, (IEEE) (2010)
• 2008
  • S. Taktak, J.‑L. Desbarbieux, E. Encrenaz : “A tool for automatic detection of deadlocks in wormhole networks on chip”, ACM Transactions on Design Automation of Electronic Systems, vol. 13 (1), pp. 1-8, (Association for Computing Machinery) (2008)
• 2006
  • S. Taktak, E. Encrenaz, J.‑L. Desbarbieux : “A Tool for Automatic Detection of Deadlock in Wormhole Networks on Chip”, HLDVT IEEE International High Level Design Validation and Test Workshop, Monterey, California, United States, pp. 203-210, (IEEE) (2006)
• 2004
  • M. Diaby, M. Tuna, J.‑L. Desbarbieux, F. Wajsbürt : “High level synthesis methodology from C to FPGA used for a network protocol communication.”, RSP 2004 - 15^th International Workshop on Rapid System Prototyping, Geneva, Switzerland, pp. 103-108, (IEEE) (2004)
• 2003
  • V. Beaudenon, E. Encrenaz, J.‑L. Desbarbieux : “Design Validation of ZCSP with SPIN”, IEEE Third International Conference on Application of Concurrency to System Design (ACSD 2003), Guimaraes, Portugal, pp. 102-110, (IEEE) (2003)
  • V. Beaudenon, E. Encrenaz, J.‑L. Desbarbieux : “Design Validation of ZCSP with SPIN”, (2003)
• 2001
  • O. Glück, A. Zerrouki, J.‑L. Desbarbieux, A. Fenyö, A. Greiner, F. Wajsbürt, C. Spasevski, F. Silva, E. Dreyfus : “Protocol and Performance Analysis of the MPC Parallel Computer”, 15^th International Parallel and Distributed Processing Symposium (IPDPS 2001), San Francisco, CA, United States, (IEEE) (2001)
• 2000
  • J.‑L. Desbarbieux : “Conception et réalisation d’un contrôleur réseau programmable pour machine parallèle de type "grappe de PC"”, thesis, defence 06/28/2000, supervision Greiner, Alain (2000)
  • A. Zerrouki, O. Glück, J.‑L. Desbarbieux, A. Fenyö, A. Greiner, C. Spasevski, F. Wajsbürt, F. Silva, E. Dreyfus : “The MPC Parallel Computer : Hardware, Low-level Protocols and Performances”, Parallel and Distributed Computing and Systems (PDCS 2000), vol. 1, Las Vegas, United States, pp. 87-92 (2000)
• 1998
  • A. Greiner, P. David, J.‑L. Desbarbieux, A. Fenyö, J.‑J. Lecler, F. Potter, V. Reibaldi, F. Wajsbürt, B. Zerrouk : “La machine MPC”, Calculateurs Paralleles Reseaux et Systemes Repartis, vol. 10 (1), pp. 71-84, (La Boucle informatique) (1998)
• 1997
  • F. Wajsbürt, J.‑L. Desbarbieux, C. Spasevski, S. Penain, A. Greiner : “An Integrated PCI Component for IEEE 1355”, European Multimedia Microprocessor Systems and Electronic Commerce Conference and Exhibition (EMMSEC'97), Florence, Italy (1997)