Dr. SHEIBANYRAD Hamed
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2006-2017 Publications
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2017
- H. Bel Hadj Amor, A. Sheibanyrad, F. PĂ©trot : “A Distributed NUCA Architecture Using an Efficient NoC Multicasting Support”, Euromicro Conference on Digital System Design (DSD 2017), Vienne, Austria, pp. 184-191, (IEEE) (2017)
- H. Bel Hadj Amor, A. Sheibanyrad, F. PĂ©trot : “A Meta-Routing Method to Create Multiple Virtual Logical Networks on a Single Hardware NoC”, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, pp. 200-205, (IEEE) (2017)
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2016
- O. Alcantara De Lima, V. Fresse, F. Rousseau, A. Sheibanyrad : “Synthesis of dependency-aware traffic generators from NoC simulation traces”, Journal of Systems Architecture, vol. 71, pp. 102-113, (Elsevier) (2016)
- P. VIVET, Y. Thonnart, R. Lemaire, C. Santos, E. Beigne, Ch. Bernard, F. Darve, D. Lattard, I. Miro‑Panades, D. Dutoit, F. Clermidy, S. ChĂ©ramy, A. Sheibanyrad, F. PĂ©trot, E. Flamand, J. Michailos, A. Arriordaz, L. Wang, J. Schloeffel : “A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links”, IEEE Journal of Solid-State Circuits, vol. 52 (1), pp. 33-49, (Institute of Electrical and Electronics Engineers) (2016)
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2014
- S. Foroutan, A. Sheibanyrad, F. PĂ©trot : “Assignment of Vertical Links to Routers in Vertically-Partially-Connected 3D-NoCs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33 (8), pp. 1208-1218, (IEEE) (2014)
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2008
- H. Sheibanyrad : “ImplĂ©mentation Asynchrone d’un RĂ©seau-sur-Puce DistribuĂ©”, thesis, defence 03/19/2008, supervision Greiner, Alain (2008)
- A. Sheibanyrad, A. Greiner : “Two Efficient Synchronous ⇔ Asynchronous Converters well-suited for Networks-on-Chip in GALS Architectures”, Integration, the VLSI Journal, vol. 41 (1), pp. 17-26, (Elsevier) (2008)
- A. Sheibanyrad, A. Greiner, I. Miro‑Panades : “Multisynchronous and Fully Asynchronous NoCs for GALS Architectures”, IEEE Design & Test, vol. 25 (6), pp. 572-580, (IEEE) (2008)
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2007
- A. Sheibanyrad, A. Greiner : “Hybrid-Timing FIFOs to use on Networks-on-Chip in GALS Architectures”, ESA International Conference on Embedded Systems and Applications, Las Vegas, Nevada, United States, pp. 27-33, (CSREA Press) (2007)
- A. Sheibanyrad, I. Miro Panades, A. Greiner : “Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture”, DATE Design Automation and Test in Europe Conference 2007, Nice, France, pp. 1090-1095, (IEEE) (2007)
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2006
- I. Miro Panades, A. Greiner, A. Sheibanyrad : “A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach”, NanoNet International Conference on Nano-Networks, Lausanne, Switzerland, pp. 1-5, (IEEE) (2006)
- A. Sheibanyrad, A. Greiner : “Two Efficient Synchronous ⇔ Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures”, International Workshop on Power And Timing Modeling Optimization and Simulation, vol. 4148, Lecture Notes in Computer Science, Montpellier, France, pp. 192-202, (Springer) (2006)
- I. Miro Panades, A. Greiner, A. Sheibanyrad : “Micro-rĂ©seau sur puce compatible avec l’approche GALS”, JournĂ©es Nationales du RĂ©seau Doctoral de Micro-Ă©lectronique, Rennes, France, pp. 1-5 (2006)