RF Receiver for Software-Defined Radio based on Bandpass Sigma-Delta Analog-to-Digital Converter
One of the main challenges in implementing a Software-Defined Radio receiver is the stringent ADC requirements. A promising technique to achieve these ADC specifications is to use a bandpass LC Sigma-Delta ADC with an RF center frequency. The first part of this research is the developing of the design methodology. A generic and simple approach to design Continuous- Time (CT) Sigma-Delta ADCs based on Finite Impulse Response Digital-to-Analog Converter (FIR DAC) is introduced. Then, a simple and robust architecture of LC-based Sigma-Delta ADCs is introduced. The excess loop delay, which usually has a negative effect on the stability and the Signal-to-Noise Ratio (SNR) of the ADC, can be used to simplify the ADC architecture and reduce the number of the needed feedback branches. The presented architecture is shown to be robust against the variations of the excess loop delay due to the process variations. The clock jitter effect is then studied. A simple and intuitive technique for analyzing clock jitter effect on CT Sigma-Delta ADCs is introduced and applied for different types of feedback DACs. Also, a fast and accurate technique for modeling and simulating the clock jitter in CT Sigma-Delta ADCs is introduced. Finally, we present an efficient realization of two RF bandpass Sigma-Delta ADCs centered at 900MHz and 2.4GHz. The two ADCs are implemented in a standard low-cost Complementary Metal-Oxide-Semiconductor (CMOS) technology. Their power consumption is significantly lower than recent realizations. Subsampling is used in the second ADC centered at 2.4GHz, to reduce the sampling frequency, while still keeping it equal to four times the output frequency.
Defence : 01/13/2012 - 10h30 - Site Jussieu - Salle des thèses de l'Atrium Jury members : B. Nauta, Professeur, Twente University, Les Pays-Bas [Rapporteur]
A. Kaiser, Directeur de recherche CNRS, ISEN-IEMN, Lille [Rapporteur]
A. Cathelin, Dr. Ing. STMicroelectronics R&D, Crolles
D. Morche, Dr. Ing. CEA-LETI, Grenoble
A. Benlarbi-Delai, Professeur UPMC
G. Klisnick, Maître de conférences UPMC
H. Mehrez, Professeur UPMC.
H. Aboushady, Maître de conférences UPMC
Ah. Ashry, H. Aboushady : “Sine-Shaping Mixer for Continuous-Time ΣΔ ADCs”, IEEE International Symposium on Circuits and Systems (ISCAS'11), Rio de Janeiro, Brazil, pp. 1113-1116, (IEEE) (2011)
Ah. Ashry, H. Aboushady : “Main Defects of LC-Based ΣΔ Modulators”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'10), Seattle, USA, pp. 897-900, (IEEE) (2010)
Ah. Ashry, H. Aboushady : “Modeling Jitter in Continuous-Time ΣΔ Modulators”, IEEE International Behavioral Modeling and Simulation Conference (BMAS'10), San Jose, CA, USA, pp. 55-58, (IEEE) (2010)
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