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ALLAM Mootaz

PhD graduated
Team : CIAN
Departure date : 11/01/2016
Supervision : Hassan ABOUSHADY

Wide-band Sigma-Delta ADC

Today's wireless communication systems are requiring high performance Converters analog-digital (ADC) with increasing demand on bandwidth and resolution. Since the market is expecting complex receiving capacities with low power battery operated devices, there is a growing need for low-power and multi-functional RF receivers. For this reason the current trend is to decrease the analogue part of the receivers, while increasing the tasks performed by the digital part. Therefore, this imposes stringent requirements on the ADC such as wideband operation, high resolution and low power consumption.
In this dissertation, we studied and realized several types of VCO-based ADCs. We show the design, the implementation and the measurement results of two types of VCO-based ADCs in 65nm CMOS process. The first is using the voltage to frequency conversion technique while the second uses the principle of voltage to phase conversion. The voltage to frequency converter is a 4-bit ADC with a programmable sampling frequency that goes from 220MHz up to 1500MHz. The measured Signal-to-noise-and-distortion-ratio (SNDR) is of 40.5dB in a band of 30MHz with a power consumption of 0.5mW.
The voltage phase converter is a 4-bit ADC with a programmable sampling frequency that goes from 300MHz up to 1440MHz. The measured SNDR is 48dB in a band of 30MHz with a consumption of 1mW. We then present a systematic design method of high order SigmaDelta ADCs with VCO-based quantizers.
To validate the design method, a SigmaDelta ADC with a 4-bit voltage-frequency is designed in 65nm. The measured SNDR is 62dB in a band of 28MHz and a power consumption of 30mw. We propose the use of VCO-based quantizers in quadrature SigmaDelta modulators. A systematic design method is presented for the quadrature VCO-based Sigmadelta modulators. A 4th order quadrature sigmadelta with 4-bit voltage to frequency quantizers is designed in 65nm. The measurements of this circuit are currently in progress. In post layout simulations, the quadrature modulator achieves 75dB in a band of 40MHz and a power consumption of 60mW.
Defence : 06/12/2015 - 13h30 - Site Jussieu 25-26/105
Jury members :
MALOBERTI Franco (Pavia U Italy)
KAISER Andreas (ISEN-IEMN, Fr)
SALAMA Khaled (KAUST U. KSA)
SABUT Marc (STMicroelectronics, Fr)
BENLARBI DELAI Aziz (L2E UPMC)

2010-2015 Publications

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