On the field Detection, De-activation and Reconfiguration (ODDR) mechanism for Permanent Fault-Tolerance of Network-on-Chip
This thesis presents a complete ODDR (“On the field” Detection, De-activation and Reconfiguration) mechanism, providing a permanent fault-tolerance for a 2D-Mesh Netw- ork-on-Chip (NoC) in a shared memory, Massively-Parallel Multi-Processors System-on- Chip (MP2SoC) architecture.
This mechanism is executed at each system reboot or chip power-on, to detect and de- activate the faulty components of NoC and to activate the fault-free components ; then it makes NoC itself to achieve a self-reconfiguration through the fault-free/activated compo- nents. In conclusion, with the help of this ODDR mechanism, a damaged 2D-Mesh NoC can structurally self-test, partially self-disable, globally self-reconfigure and functionally self-recover, after a simple system reboot or at chip power-on. Moreover, this mechanism can be used in any 2D-Mesh NoC based, shared memory, multi-cores architecture.
The ODDR mechanism has been implemented in a typical 2D-Mesh NoC : DSPIN. Thanks to this micro-network, we evaluate and analyze the mechanism, from the point of view of the stuck-at fault coverage, of the silicon area overhead, of the execution time consumed, etc.
It should be noted that, the ODDR mechanism can be used not only “on the field”, but also in the manufacture, where it’s helpful to improve the yield by avoiding to throw the whole chip when one single component is faulty.
Defence : 06/27/2011 - 14h00 - Site Jussieu, Amphi ASTIER du bâtiment Esclangon Jury members : ANGHEL Lorena, Professeur, TIMA [Rapporteur]
ROUZEYRE Bruno, Professeur, LIRMM [Rapporteur]
COPPOLA Marcello, Ingénieur, STMicroelectronics
MARINISSEN Erik Jan, Ingénieur, IMEC vzw - Belgium
SENS Pierre, Professeur, UPMC
GREINER Alain, Professeur, UPMC
BENABDENBI Mounir, Maître de conférences, TIMA