Team : CIAN
Departure date : 09/01/2013
Supervision : Habib MEHREZ
Placement and routing tools to secure FPGA architectures against DPA attacks
Nowadays, most of the data computing has become digital, thereby increasing the need for security and subsequent use of cryptography. Cryptographic algorithms have traditionally been studied to withstand mathematical attacks. However, when these algorithms are implemented on electronic devices, these cryptographic systems become potential targets of attacks. One of the most dangerous attacks is the Differential Power Analysis attack which exploits the power consumption leaked by a cryptographic device to extract the secret key. The dual rail precharge logic techniques such as the WDDL method are a promising solutions to increase the robustness of secure devices against this attack. They make the circuit activity constant and uncorrelated to the processed data. Nevertheless, to guarantee the effectiveness of this approach, the routing of dual signals of the design must be carefully balanced.
This thesis deals with the problem of dual signals balance in WDDL design implemented on FPGA architectures. Initially, we focus on a tree based FPGA architecture, called MFPGA. We propose and compare partitioning and placement techniques to reduce the unbalance of dual signals. Then, we propose a new Timing-Balance-Driven routing algorithm, whose goal is to balance the routing of dual signals in terms of delay propagation. Based on the Elmore delay model, results show that our new placement and routing tools have improved the delay unbalance by 93%.
Besides, we target a Mesh based FPGA architecture. First, we adapt dual placement and Timing-Balance-Driven routing techniques to an island style architecture, and we obtain a gain of 90% of delay balance. Then, we propose a differential pair routing approach for a cluster based FPGA architecture. This technique achieves better results, but it has the disadvantage of depending on the characteristics of the FPGA architecture.
After that, we propose a new Timing-Balance-Driven routing algorithm, which is architecture independent, and we show its efficiency in tree based and mesh based FPGAs. We note that the remaining delay unbalance in MFPGA is due to the unbalance between architecture routing wires. Finally, we target a new hierarchical FPGA architecture, called Mesh of Tree, which allows to reduce the unbalance related to the architecture. We show that we can obtain better delay balance results with the Mesh of Tree architecture, by adding to the routing algorithm a constraint which is related to the architecture characteristics.
Defence : 09/30/2011 - 14h00 - Site Jussieu - Bat 41 - Salle 203/205 Jury members : M. Gilles SASSATELLI, LIRMM [Rapporteur]
M. Guy GOGNIAT, Lab-STICC [Rapporteur]
M. Jean-Claude BAJARD, UPMC
M. Laurent FESQUET, TIMA
M. Yves MATHIEU, ENST
M. Habib MEHREZ, UPMC
A. Ben Dhia, S. Ur Rehman, A. Blanchardon, L. Naviner, M. Benabdenbi, R. Chotin‑Avot, H. Mehrez, E. Amouri, Z. Marrakchi : “A Defect-tolerant Cluster in a Mesh SRAM-based FPGA”, International Conference on Field-Programmable Technology (FPT), Kyoto, Japan, pp. 434-437, (IEEE) (2013)