Team : ALSOC
Departure date : 07/01/2011
: Alain GREINER
Generic cache controller for a massively parallel manycore architecture with coherent shared memory
In order to support commodity O.S. in the scalable many-core shared memory architecture, virtual memory and cache coherence protocol are imperative. The former is the basic technique to provide the isolation and the protection in the modern computers, when running in parallel a large number of programs. The latter is the key issue to run parallel cooperative(multi-thread) applications on a shared memory system.
Studies show that most of existent cache coherence protocols use hardware solutions, while almost all the TLB consistency protocols rely on software methods which ensures the TLB coherence by sending interrupts to all processors that have this TLB entry copy. However when massive tasks execute in parallel in tera scale architecture, a mass of interrupts can dramatically reduce the performance. So the classical software TLB consistency protocols are not a scalable solution for tera scale system.
In this thesis, we propose a combined hardware approach to guarantee both TLB and cache coherence for tera scale architecture while only introducing very light hardware cost. We developed two hardware structures based on this approach. They provide alternatives for low coherence overhead or low hardware complexity respectively. The experimental results demonstrate that our combined hardware coherence approach is scalable in both hardware cost and performance.
: 06/28/2011 - 14h00 - Amphi ASTIERJury members
SEZNEC André , Directeur de recherche, IRISA [Rapporteur]
TEMAM Olivier , Directeur de recherche, INRIA Saclay [Rapporteur]
PETROT Frédéric , Professeur, TIMA
SHAPIRO Marc, Directeur de recherche, LIP6
NGUYEN Huy-Nam, Responsable du Département IP/SDD/MVS, Bull
GREINER Alain , Professeur, LIP6