Conversion analogique-numerique Basse-Consommation pour Micro-Capteurs
In the context of an analog front end for a high-density memory composed of Micro-Electro-Mechanical Structures (MEMS) micro-cantilevers, there are severe constraints on the area and power consumption of the analog-to-digital converter. In this work, several ADC architectures targeting 7bits of resolution and 50kHz of bandwidth while occupying an active area less than 0.1mm2 and a power consumption less than 200uW, have been investigated. A Switched-Capacitor Sigma-Delta, a Continuous-Time Sigma-Delta and a Cyclic ADC have been designed, fabricated and measured.
Systematic design procedure for the circuit synthesis and the automatic layout generation of a low-power ADC has been developed in the CAIRO+ analog design automation environment.
Defence : 09/29/2008 - 14h - Campus Jussieu, Atrium, Salle RC 27 Jury members : - Pr. Hervé Barthelémy, Universite Marseille III,France. President du
- Pr. Piero Malcovati, Universite de Pavie, Italie. Rapporteur.
- Pr. Pieter Rombouts, Universite de Gand, Belgique. Rapporteur.
- Dr. Cyril Condemine, CEA-LETI, France. Examinateur.
- Dr. Christoph Hagleitner, IBM-Zurich, Suisse. Examinateur.
- Pr. Alain Greiner, UPMC, France. Directeur de These.
- Dr. Marie-Minerve Louerat, UPMC, France. Co-encadrante.
- Dr. Hassan Aboushady, UPMC, France. Encadrant academique.