DUMONTEIX Yannick
Supervision : Habib MEHREZ
Optimisation des chemins de données arithmétiques par l'utilisation de plusieurs systèmes de numération
Defence : 10/10/2001
Jury members :
Alain Guyot - rapporteur
M. Daumas - rapporteur
Alain Greiner
Habib Mehrez
Michel Robert
Jean-Marie Cheneaux
2000-2001 Publications
-
2001
- Y. Dumonteix : “Optimisation des chemins de données arithmétiques par l’utilisation de plusieurs systèmes de numération”, thesis, phd defence 10/10/2001, supervision Mehrez, Habib (2001)
- H. Aboushady, Y. Dumonteix, M.‑M. Louërat, H. Mehrez : “Efficient Polyphase decomposition of Comb decimation filters in sigma-delta analog-to-digital converters”, IEEE Transactions on Circuits and Systems Part 2 Analog and Digital Signal Processing, vol. 48 (10), pp. 898-903, (Institute of Electrical and Electronics Engineers (IEEE)) (2001)
- Y. Dumonteix, Y. Bajot, H. Mehrez : “A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic”, IEEE International Symposium on Circuits and Systems (ISCAS'2001), vol. 4, Sydney, Australia, pp. 878-881, (IEEE) (2001)
-
2000
- Y. Dumonteix, H. Aboushady, H. Mehrez, M.‑M. Rosset‑Louërat : “Low-power Comb Decimation Filter Using Polyphase Decomposition For Mono-bit Sigma-Delta Analog-to-Digital Converters”, International Conference On Signal Processing Applications and Technologies (ICSPAT 2000), vol. 1, Dallas, Texas, United States, pp. 432-435 (2000)
- H. Aboushady, Y. Dumonteix, M.‑M. Rosset‑Louërat, H. Mehrez : “Efficient Polyphase Decomposition of Comb Decimation Filters in Sigma-Delta Analog-to-Digital Converters”, 43rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2000), Lansing, MI, United States, pp. 432-435, (IEEE) (2000)
- Y. Dumonteix, H. Mehrez : “A family of redundant multipliers dedicated to fast computation for signal processing”, IEEE International Symposium on Circuits and Systems (ISCAS 2000), vol. 5, Geneva, Switzerland, pp. 325-328, (IEEE) (2000)
- R. Chotin, Y. Dumonteix, H. Mehrez : “Use of Redundant Arithmetic on Architecture and Design of a High Performance DCT Macro-bloc Generator”, 15th Design of Circuits and Integrated Systems Conference (DCIS), Montpellier, France, pp. 428-433 (2000)