The rapid expansion of data-intensive applications, ranging from High-Performance Computing and Artificial Intelligence to embedded and automotive systems, has created an unprecedented demand for computing architectures that are simultaneously high-performance, energy-efficient, flexible, secure, and sustainable. As modern Systems-on-Chip integrate billions of transistors and increasingly heterogeneous processing elements, their design spaces grow combinatorially, making exhaustive exploration impractical. This increasing complexity raises a central question that has guided my research: How can we efficiently design computing systems capable of processing ever larger volumes of data while meeting these increasingly stringent requirements?
This Habilitation progressively establishes an optimization-driven hardware/software co-design methodology in which Operations Research and Combinatorial Optimization evolve from solving application-level scheduling problems to becoming the quantitative decision engine of the complete hardware/software design process. It first develops mathematical models and scalable optimization techniques for mapping and scheduling parallel applications on heterogeneous architectures. The methodology is then extended to architecture design through VPSim, a fast virtual prototyping platform providing an effective trade-off between simulation accuracy and execution speed, and A-DECA, an automated Design Space Exploration framework enabling efficient multi-objective optimization of heterogeneous computing systems.
Building upon these foundations, optimization is further extended to the complete Electronic Design Automation (EDA) flow, where it orchestrates architecture exploration, RTL generation, synthesis, and physical implementation. Beyond improving design quality, this automation also increases engineering productivity by accelerating design-space exploration and reducing development time. The same quantitative approach is finally extended to hardware security, through optimization models that automatically integrate security countermeasures during logic synthesis.
The long-term ambition of this research is to transform hardware/software co-design into a fully quantitative optimization process, where architectural decisions are systematically guided by mathematical modeling, simulation, and optimization. The methodological foundations established throughout this work naturally extend toward emerging heterogeneous RISC-V architectures, chiplet-based integration, and silicon-photonic interconnects. Hybrid Operations Research/Artificial Intelligence optimization and sustainability-aware design further broaden this methodology toward the next generation of computing architectures.