# FONTAINE Jonathan

Team : CIAN
Departure date : 05/24/2024
https://lip6.fr/Jonathan.Fontaine

Supervision : Roselyne CHOTIN

Co-supervision : ZAOURAR Lilia

# Optimization of the insertion of countermeasures for the security of Integrated Circuits

Over the last 75 years, the electronics industry has experienced a spectacular evolution, moving from manual design to an automated industry. This industrialization has led to increased complexity in circuits, requiring specialization in tasks during the design of electronic circuits. Various companies around the world have emerged to perform these tasks, with varying levels of trust assigned. From a designerâ€™s perspective, these actors pose several threats, such as the insertion of malicious functionalities, intellectual property theft, or circuit counterfeiting. These threats impact the economy of the semiconductor industry, amounting to billions of dollars in losses annually.
One way to combat these threats is to lock the circuit with a key, preventing it from functioning correctly if the right key is not present. Logic locking is a method that involves logically locking a circuit using key gates and the corresponding digital key. Several implementations of logic locking have been developed. In these works, we focus on Strong Logic Locking. It locks the circuit by connecting XOR/XNOR gates to the digital key, inserted in circuit signals. Each insertion position has a different impact on security, which is the possibility of recovering the digital key. However, adding logic gates in a circuit increases power consumption, the circuitâ€™s area, and decreases performance. Strong logic locking aims to maximize the security of the lock by identifying positions that enhance security, regardless of the resulting impact. In this thesis, we seek to optimize security while considering the impact on circuit performance. We propose a new approach to solving strong logic locking. We start by formulating our security problem based on mathematical models that include security for optimally inserting key gates in the circuit. This formulation calculates the cliques of a subgraph representing the insertion positions. We establish a branch and bound solving algorithm for our problem and evaluate it. We then present a second mathematical model representing the impact on the delay from inserting key gates in the circuit. Finaly, we propose strategies to optimize security while limiting the impact on circuit performance. Our tools are integrated into the design flow, allowing us to validate them with numerical results obtained on circuits used by the electronic community.

Defence : 05/24/2024

## Jury members :

Philippe COUSSY, Professeur, Université de Bretagne Sud, LAB-STICC [Rapporteur]
André ROSSI, Professeur, Université Paris-Dauphine, LAMSADE [Rapporteur]
Sophie DUPUIS, Maîtresse de Conférences, Université de Montpellier, LIRMM Eaminatrice
Alix MUNIER, Professeure, Sorbonne Université, LIP6
Ozgur SINANOGLU, Professeur, New York University Abu Dhabi
Gabriel GOUVINE, Ingénieur, Autoentrepreneur
Lilia ZAOURAR, Ingénieur de Recherche, CEA-LIST, DSCIN
Roselyne CHOTIN, Maître de Conférences, Sorbonne Université, LIP6

Departure date : 05/24/2024