PhD graduated
Team : CIAN
Departure date : 10/08/2014

Supervision : Habib MEHREZ

Co-supervision : CHOTIN Roselyne

Authenticated Encryption on FPGAs from the Reconfigurable Part to the Static Part

Communication systems need to access, store, manipulate, or communicate sensitive information. Therefore, cryptographic primitives such as hash functions and block ciphers are deployed to provide encryption and authentication. Recently, techniques have been invented to combine encryption and authentication into a single algorithm which is called Authenticated Encryption (AE). Combining these two security services in hardware produces better performance compared to two separated algorithms since authentication and encryption can share a part of the computation. Because of combining the programmability with the performance of custom hardware, FPGAs become more common as an implementation target for such algorithms.
The first part of this thesis is devoted to efficient and high-speed FPGA-based architectures of AE algorithms, AES-GCM and AEGIS-128, in order to be used in the reconfigurable part of FPGAs to support security services of communication systems. Our focus on the state of the art leads to the introduction of high-speed architectures for slow changing keys applications like Virtual Private Networks (VPNs). Furthermore, we present an efficient method for implementing the GF(2^128) multiplier, which is responsible for the authentication task in AES-GCM, to support high-speed applications. Additionally, an efficient AEGIS-128 is also implemented using only five AES rounds. Our hardware implementations were evaluated using Virtex-5 and Virtex-4 FPGAs. The performance of the presented architectures (Thr./Slices) outperforms the previously reported ones.
The second part of the thesis presents techniques for low cost solutions in order to secure the reconfiguration of FPGAs. We present different ranges of low cost implementations of AES-GCM, AES-CCM, and AEGIS-128, which are used in the static part of the FPGA in order to decrypt and authenticate the FPGA bitstream. Presented ASIC architectures were evaluated using 90 and 65 nm technologies and they present better performance compared to the previous work.

Defence : 10/07/2014 - 10h30 - Site Jussieu 25-26/105

Jury members :

Bruno ROBISSON, Chercheur, CEA [Rapporteur]
Lilian BOSSUET, MCF, Univ. ST ETIENNE [Rapporteur]
Jean-Claude BAJARD, Professeur, UPMC
Hayder MRABET, Industriel, Phd
Olivier Lepape, NanoXplore
Habib MEHREZ, Professeur, UPMC

2012-2016 Publications