Supervision : Laurent-Stéphane DIDIER

Co-supervision : HILAIRE Thibault

Optimal Filter Implementation in Fixed Point Arithmetic

Embedded systems implement signal processing systems, such as linear filters, for example for communication through networks. These devices are subject to various constraints, such as power consumption, time-to-market, area consumption, and so on, that is necessary to optimize while guaranteeing reliability and accuracy of the implemented systems. Fixed-point arithmetic is generally used instead of floating-point arithmetic for signal processing embedded systems because it is less expensive, all devices support fixed-point numbers (as they are implemented only using integers), allows arbitrary word-lengths in hardware implementation and is enough accurate for signal processing programs. Fixed-point computations need the operands of an operation to be aligned together with the same position of the binary point. This leads to quantification errors and the goal is to minimize these round-off effects onto the final result, by proposing a guarantee on the output error. During this thesis, a methodology has been proposed which implements a given algorithm in fixed-point using analytical approach, and generates some codes. This methodology consider both software and hardware targets. The hardware approach is realized solving a word-length optimization problem. A tool, named FiPoGen, has been developed that realizes this methodology and automatically yields fixed-point code corresponding to a given filter algorithm with a guarantee on the output error.

2012-2019 Publications

• 2019
  • Th. Hilaire, H. Ouzia, B. Lopez : “Optimal Word-Length Allocation for the Fixed-Point Implementation of Linear Filters and Controllers”, ARITH 2019 - IEEE 26^th Symposium on Computer Arithmetic, Kyoto, Japan, pp. 175-182, (IEEE) (2019)
• 2015
  • B. Lopez : “Implémentation optimale de filtres linéaires en arithmétique virgule fixe: Présentation au séminaire CAIRN, Rennes”, (2015)
• 2014
  • B. Lopez : “Implémentation optimale de filtre en arithmétique virgule fixe”, thesis, phd defence 11/27/2014, supervision Didier, Laurent-Stéphane, co-supervision : Hilaire, Thibault (2014)
  • B. Lopez, Th. Hilaire, L.‑S. Didier : “Formatting bits to better implement signal processing algorithms”, 4^th international Conference on Pervasive and Embedded Computing and Communication Systems (PECCS), Lisbon, Portugal, pp. 104-111, (ScitePress) (2014)
• 2013
  • Th. Hilaire, B. Lopez : “Reliable implementation of linear filters with fixed-point arithmetic”, Signal Processing Systems (SiPS), Taipei, Taiwan, Province of China, pp. 401-406 (2013)
• 2012
  • B. Lopez, Th. Hilaire, L.‑S. Didier : “Sum-of-products Evaluation Schemes with Fixed-Point arithmetic, and their application to IIR filter implementation”, Conference on Design and Architectures for Signal and Image Processing (DASIP), Karlsruhe, Germany (2012)
  • D. Ménard, R. Rocher, O. Sentieys, N. Simon, L.‑S. Didier, Th. Hilaire, B. Lopez, E. Goubault, S. Putot, F. Vedrine, M. Najahi, G. Revy, L. Fangain, Ch. Samoyeau, F. Lemonnier, Ch. Clienti : “Design of Fixed-Point Embedded Systems (defis) French ANR Project”, DASIP: Design and Architectures for Signal and Image Processing, Karlsruhe, Germany, pp. 365-366 (2012)