PhD graduated
Team : CIAN
Departure date : 11/24/2014

Supervision : Habib MEHREZ

Co-supervision : MARRAKCHI Zied

High Performance Three-Dimensional Tree-based FPGA Architecture using 3D Technology Process

Today, FPGAs (Field Programmable Gate Arrays) has become important actors in the computational devices domain that was originally dominated by microprocessors and ASICs. FPGA design big challenge is to need a good trade-off between flexibility and performances. Three factors are combined to determine the characteristics of an FPGA: quality of its architecture, quality of the CAD tools used to map circuits into the FPGA, and its electrical technology design. This dissertation aims at exploring a development of Three- dimensional (3D) physical design methodology and exploration tools for 3D Tree-based stacked FPGA architecture to improve area, density, power and performances.
The first part of the dissertation is to study the existing variants of 2D Tree-based FPGA architecture and the impact of 3D migration on its topology. We have seen numerous studies showing the characteristics of Tree-based interconnect networks, how they scale in terms of area and performance, and empirically how they relate to particular designs. Nevertheless we never had any breakthrough in optimizing these network topologies to exploit the advantages in area and power consumption and how to deal with the larger wire-length issues that impede performance of Tree-based FPGA architecture. Through the course of the work, we understand that, we would not be able to optimize the speed, unless we break the very backbone of the Tree-based interconnect network and resurrect again by using 3D technology. The 3D-ICs can alleviate interconnect delay issues by ofering exibility in system design, placement and routing. A new set of 3D FPGA architecture exploration tools and technologies developed to validate the advance in performance and area.
The second contribution of this thesis is the development 3D physical design methodology and tools using existing 2D CAD tools for the implementation of 3D Tree-based FPGA demonstrator. During the course of design process, we addressed many specic issues that 3D designers will encounter dealing with tools that are not specically designed to meet their needs. In contrast, the thermal performance is expected to worsen with the use of 3D integration. We examined precisely how thermal behavior scales in 3D integration and determine how the temperature can be controlled using thermal design techniques.

Defence : 11/24/2014

Jury members :

M. GOGNIAT Guy : Professeur, Université Bretagne-Sud [Rapporteur]
M. SASSATELLI Gilles : Maître de conférence (HDR), Université Montpellier [Rapporteur]
M. GREINER Alain : Professeur, LIP6
M. MEHREZ Habib : Professeur, LIP6
M. Marrakchi Zied: CTO FLEXRAS Technologies

Departure date : 11/24/2014

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