GIDRA Lokesh

Équipe : REGAL
Date de départ : 28/09/2015

Direction de recherche : Marc SHAPIRO

Co-encadrement : THOMAS Gaël, MULLER Gilles

Ramasse-miettes pour les machines virtuelles sur les processeurs multicoeurs

Large-scale multicore architectures create new challenges for garbage collectors (GCs). On contemporary cache-coherent Non-Uniform Memory Access (ccNUMA) architectures, applications with a large memory footprint suffer from the cost of the garbage collector (GC), because, as the GC scans the reference graph, it makes many remote memory accesses, saturating the interconnect between memory nodes. In this thesis, we address this problem with NumaGiC, a GC with a mostly-distributed design.
In order to maximise memory access locality during collection, a GC thread avoids accessing a different memory node, instead notifying a remote GC thread with a message; nonetheless, NumaGiC avoids the drawbacks of a pure distributed design, which tends to decrease parallelism and increase memory access imbalance, by allowing threads to steal from other nodes when they are idle. NumaGiC strives to find a perfect balance between local access, memory access balance, and parallelism.
In this work, we compare NumaGiC with Parallel Scavenge and some of its incrementally improved variants on two different ccNUMA architectures running on the Hotspot Java Virtual Machine of OpenJDK 7. On Spark and Neo4j, two industry-strength analytics applications, with heap sizes ranging from 160 GB to 350 GB, and on SPECjbb2013 and SPECjbb2005, NumaGiC improves overall performance by up to 94% over Parallel Scavenge, and increases the performance of the collector itself by up to 5.4× over Parallel Scavenge. In terms of scalability of GC throughput with increasing number of NUMA nodes, NumaGiC scales substantially better than Parallel Scavenge for all the applications. In fact in case of SPECjbb2005, where inter-node object references are the least among all, NumaGiC scales almost linearly.

Soutenance : 28/09/2015 - 13h30 - Site Jussieu 25-26/105

Membres du jury :

M. Vivien Quema, Grenoble INP/ENSIMAG [Rapporteur]
M. Luis Veiga, Instituto Superior Técnico - ULisboa | INESC-ID Lisboa [Rapporteur]
M. Albert Cohen, Département d'Informatique - ENS/INRIA
M. Tim Harris, Oracle Labs, Cambridge
M. Marc Shapiro, Université Pierre et Marie Curie (LIP6/INRIA)
M. Gaël Thomas, Telecom SudParis (HPS)

Publications 2011-2015