CBackground Analog and Mixed Signal Calibration System For Time-Interleaved ADC
In this work, we present a Time-Interleaved ADC (TIADC) calibration technique for four different types of mismatches (offset, gain, time skew and bandwidth). The mismatches and the calibration technique are analysed analytically. The calibration operates in background mode using a novel technique. The calibration system is an analog mixed one where the error detection is performed digitally by three detectors: one for the offset, one for the amplitude and one for the phase. The corrections of the time skew and the bandwidth mismatches depend on a Digitally Controlled Delay Line and a tunable switch resistor respectively. These analog techniques are designed on a ST CMOS 40 nm technology. A calibration sequence is presented which helps to distinguish between the different errors to perform the error detection correctly. The efficiency and the accuracy of the calibration technique are illustrated by the system level simulations. The calibration system architecture and specifications for a 4 channel, 12 bit, 800 MS/s TIADC are presented. It consists of two parts: the Analog Mixed sub-system (AMS sub-system) where the correction of errors takes place and the digital sub-system where the control sequence and error detection take place. The digital sub-system is implemented using an FPGA in order to have a reconfigurable platform suitable for testing different TIADCs. The interface technique between the FPGA and the AMS sub-system is presented. Simulation of the whole system showing the efficiency of the approach is presented.
Defence : 09/16/2013 - 14h30 - Site Jussieu 25-26/105 Jury members : Pr. Van Juijl, Université de Twente, Pays Bas, rapporteur
Andreas Kaiser, IEMN, France, Lille, rapporteur
Roger Petigny, STMicroelectronics, France, Grenoble
Hassan Aboushady, UPMC
Pr.Habib Mehrez, UPMC
Dr.Marie-Minerve Louerat, UPMC