CIAN - Conference papers

Current teams :	ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL
Former team :	ACASA

Publications CIAN	2023	2024	Total
Books	0	0	0
Edited books	0	0	0
Journal articles	7	1	8
Book chapters	1	0	1
Conference papers	6	2	8
Habilitations	0	0	0
Thesis	2	1	3

LIP6

H. Adel, M.‑M. Louërat, M. Sabut : “Design Considerations for Low Gain Amplifier in the MDAC of Digitally Calibrated Pipelined ADCs”, IFIP/IEEE 21^st International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, pp. 23-26, (IEEE) [Adel 2013]
E. Amouri, A. Blanchardon, R. Chotin‑Avot, H. Mehrez, Z. Marrakchi : “Efficient Multilevel Interconnect Topology for Cluster-based Mesh FPGA Architecture”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) [Amouri 2013a]
L. Andrade Porras, T. Maehne, M.‑M. Louërat, F. Pêcheux : “Time Step Control and Threshold Crossing Detection in SystemC AMS 2.0”, Actes du huitième colloque du GDR SOC-SIP du CNRS, Lyon, France, pp. 3 [Andrade Porras 2013]
P. Bazargan Sabet, D. Le Dû : “Identifying Signal Correlations Using Discrete Event Simulation”, IEEE International New Circuits and Systems Conference, Paris, France, pp. 349-352 [Bazargan Sabet 2013]
N. Belhadj, N. Bahri, M. Ali Ben Ayed, Z. Marrakchi, H. Mehrez : “Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC”, 2013 10^th International Multi-Conference on Systems, Signals & Devices (SSD), Hammamet, Tunisia, (IEEE) [Belhadj 2013]
A. Ben Dhia, S. Ur Rehman, A. Blanchardon, L. Naviner, M. Benabdenbi, R. Chotin‑Avot, H. Mehrez, E. Amouri, Z. Marrakchi : “A Defect-tolerant Cluster in a Mesh SRAM-based FPGA”, International Conference on Field-Programmable Technology (FPT), Kyoto, Japan, pp. 434-437, (IEEE Computer Society) [Ben Dhia 2013b]
E. Blokhina, D. Fournier‑Prunaret, P. Harte, D. Galayko, O. Feely : “Combined mechanical and circuit nonlinearities in electrostatic vibration energy harvesters”, Circuits and Systems (ISCAS), 2013 IEEE International Symposium on, Beijing, China, pp. paper id 1118 [Blokhina 2013a]
J. Chae, P. Mougeat, J.‑A. Francois, R. Chotin‑Avot, H. Mehrez : “Formalisme de la spécification de la plateforme de conception pour le développement de la bibliothèque”, Journees Nationales du Reseau Doctoral de Micro-electronique, Grenoble, France, pp. 1-4 [Chae 2013a]
J. Chae, S. Bertrand, P.‑F. Ollagnon, P. Mougeat, J.‑A. Francois, R. Chotin‑Avot, H. Mehrez : “Efficient State-Dependent Power Model for Multi-bit Flip-Flop Banks”, IEEE International Midwest Symposium on Circuits and Systems, Columbus, United States, pp. 461-464, (IEEE) [Chae 2013b]
F. Cottone, Ph. Basset, R. Guillemet, D. Galayko, F. Marty, T. Bourouina : “Bistable multiple-mass elecrostatic generator for low-frequency vibration energy harvesting”, Micro Electro Mechanical Systems (MEMS), 2013 IEEE 26^th International Conference on, taipei, Taiwan, Province of China [Cottone 2013a]
F. Cottone, Ph. Basset, R. Guillemet, D. Galayko, F. Marty, T. Bourouina : “Non-linear MEMS electrostatic kinetic energy harvester with a tunable multistable potential for stochastic vibrations”, Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS & EUROSENSORS XXVII), 2013 Transducers & Eurosensors XXVII: The 17^th International Conference on, barcelona, Spain [Cottone 2013b]
A. Dudka, D. Galayko, Ph. Basset : “IC design of an adaptive high-voltage electrostatic vibration energy harvester”, Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2013 Symposium on, Barcelona, Spain [Dudka 2013a]
A. Dudka, Ph. Basset, F. Cottone, E. Blokhina, D. Galayko : “Wideband Electrostatic Vibration Energy Harvester (e-VEH) Having a Low Start-Up Voltage Employing a High-Voltage Integrated Interface”, The 13^th International Conference on Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS 2013), vol. 476, Journal of Physics: Conference Series, London, United Kingdom, pp. 012127, (IOS Publishing) [Dudka 2013b]
D. Fujimoto, N. Miura, M. Nagata, Y. Hayashi, N. Homma, Y. Hori, T. Katashita, K. Sakiyama, Th. Le, J. Bringer, P. Bazargan Sabet, J.‑L. Danger : “On-Chip Power Noise Measurements of Cryptographic VLSI Circuits and Interpretation for Side-Channel Analysis”, International Symposium on Electromagnetic Compatibility (EMC Europe), Brugge, Belgium, pp. 405-410, (IEEE) [Fujimoto 2013]
D. Galayko, E. Blokhina : “Nonlinear effects in electrostatic vibration energy harvesters: Current progress and perspectives”, Circuits and Systems (ISCAS), 2013 IEEE International Symposium on, Beijing, China [Galayko 2013a]
D. Galayko, E. Blokhina, Ph. Basset, F. Cottone, A. Dudka, E. O'Riordan, O. Feely : “Tools for Analytical and Numerical Analysis of Electrostatic Vibration Energy Harvesters: Application to a Continuous Mode Conditioning Circuit”, Journal of Physics: Conference Series, London, United Kingdom, (IOP Publishing) [Galayko 2013b]
R. Guillemet, Ph. Basset, D. Galayko, F. Cottone, F. Marty, T. Bourouina : “Wideband MEMS electrostatic vibration energy harvesters based on gap-closing interdigited combs with a trapezoidal cross section”, Micro Electro Mechanical Systems (MEMS), 2013 IEEE 26^th International Conference on, Taipei, Taiwan, Province of China [Guillemet 2013]
F. Javid, R. Iskander, M.‑M. Louërat, F. Durbin : “A Structured DC Analysis Methodology for Accurate Verification of Analog Circuits”, IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, pp. 2662-2665, (IEEE) [Javid 2013a]
Y. Moursy, S. Afara, P. Buccella, C. Stefanucci, R. Iskander, M. Kayal, J.‑M. Sallese, M.‑M. Louërat, J.‑P. Chaput, M. Thomas Tomasevic , S. Ben Dhia, A. Boyer, B. Guegan, V. Poletto, A. Roggero, T. Cavioni, E. Novarini, Eh. Seebacher, A. Steinmair, P. Tisserand, D.‑M. Ton, Th. Bousquet, Th. Gneiting : “AUTOMICS: A novel approach for substrate modeling for Automotive applications”, 18^th IEEE European Test Symposium, Avignon, France [Moursy 2013]
K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “High Speed Authenticated Encryption for Slow Changing Key Applications Using Reconfigurable Devices”, Wireless Days (WD), 2013 IFIP, Valencia, Spain, pp. 1-6 [Moussa Ali Abdellatif 2013a]
K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Improved Method for Parallel AES-GCM Cores Using FPGAs”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-4, (IEEE) [Moussa Ali Abdellatif 2013b]
K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Lightweight and Compact Solutions for Secure Reconfiguration of FPGAs”, International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-4, (IEEE) [Moussa Ali Abdellatif 2013c]
K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Protecting FPGA Bitstreams Using Authenticated Encryption”, 11^th IEEE International Conference of New Circuits and Systems (NEWCAS), Paris, France, pp. 1-4, (IEEE) [Moussa Ali Abdellatif 2013d]
B. Ouattara, L. Doyen, D. Ney, H. Mehrez, P. Bazargan‑Sabet, F. Bana : “Redundancy Method to assess Electromigration Lifetime in power grid design”, IEEE International Interconnect Technology Conference (IITC),, Kyoto, Japan, pp. 81-83, (IEEE) [Ouattara 2013]
V. Pangracious, E. Amouri, H. Mehrez, Z. Marrakchi : “Physical Design Exploration of 3D Tree-based FPGA Architecture”, GLSVLSI'13 - The 23rd ACM international conference on Great lakes symposium on VLSI, Paris, France, pp. 335-336, (ACM) [Pangracious 2013a]
V. Pangracious, H. Mehrez, N. Beltaief, Z. Marrakchi, U. Farooq : “Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA)”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) [Pangracious 2013b]
V. Pangracious, H. Mehrez, U. Farooq, Z. Marrakchi : “High Performance 3-Dimensional Heterogeneous Tree-based FPGA Architectures (HT-FPGA)”, FPGAworld'13 - The 10^th FPGAworld Conference, Stockholm, Sweden, pp. 3:1-3:6, (ACM) [Pangracious 2013c]
V. Pangracious, H. Mehrez, Z. Marrakchi : “Architecture Level TSV Count Minimization Methodology for 3D Tree-based FPGA”, Cool Chips XVI, Yokohama, Japan, pp. 1-3, (IEEE) [Pangracious 2013d]
V. Pangracious, H. Mehrez, Z. Marrakchi : “Designing 3D tree-based FPGA: Interconnect Optimization and Thermal Analysis”, NEWCAS'13 - IEEE 11^th International Conference on New Circuits and Systems, Paris, France, pp. 1-4, (IEEE) [Pangracious 2013e]
V. Pangracious, H. Mehrez, Z. Marrakchi : “Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology”, IEEE International 3D Systems Integration Conference (3DIC), 2013, San Francisco, CA, United States, pp. 1-8, (IEEE) [Pangracious 2013f]
V. Pangracious, H. Mehrez, Z. Marrakchi : “TSV count minimization and thermal analysis for 3D Tree-based FPGA”, ICICDT 2013 - International Conference on IC Design & Technology, Pavia, Italy, pp. 223-226, (IEEE) [Pangracious 2013g]
V. Pangracious, Z. Marrakchi, E. Amouri, H. Mehrez : “Performance analysis and optimization of high density tree-based 3d multilevel FPGA”, Reconfigurable Computing: Architectures, Tools and Applications, vol. 7806, Lecture Notes in Computer Science, Los Angeles, CA, United States, pp. 197-209, (Springer) [Pangracious 2013h]
V. Pangracious, Z. Marrakchi, H. Mehrez : “Design and optimization of heterogeneous tree-based FPGA using 3D technology”, FPT 2013 - International Conference on Field-Programmable Technology, Kyoto, Japan, pp. 334-337, (IEEE) [Pangracious 2013i]
Ch. Shan, D. Galayko, F. Anceau : “On-chip clock error characterization for clock distribution system”, VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on, Natal, Brazil, pp. 102-108 [Shan 2013a]
Ch. Shan, E. Zianbetov, W. Yu, F. Anceau, O. Billoint, D. Galayko : “FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation”, Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, Cancun, Mexico, pp. 1-6 [Shan 2013b]
Q. Tang : “Flot de Conception Automatique pour Créer une Carte Multi-FPGA”, Journées Nationales du Réseau Doctoral en Microélectronique, Grenoble, France [Tang 2013a]
Q. Tang, M. Tuna, H. Mehrez : “Routing algorithm for multi-FPGA based systems using multi-point physical tracks”, RSP 2013 - 24^th IEEE International Symposium on Rapid System Prototyping, Montreal, Canada, pp. 2-8, (IEEE) [Tang 2013b]
Q. Tang, M. Tuna, Z. Marrakchi, H. Mehrez : “Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist”, Proceedings of the 9^th International Symposium on Applied Reconfigurable Computing, ARC 2013, vol. 7806, Lecture Notes in Computer Science, Los Angeles, United States, pp. 221, (Springer) [Tang 2013c]
M. Turki, H. Mehrez, Z. Marrakchi, M. Abid : “Partitioning constraints and signal routing approach for multi-FPGA prototyping platform”, ISSoC 2013 - International Symposium on System on Chip, Tampere, Finland, pp. 1-4, (IEEE) [Turki 2013a]
M. Turki, Z. Marrakchi, H. Mehrez, M. Abid : “Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform”, ARC 2013 - 9^th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, vol. 7806, Lecture Notes in Computer Science, Los Angeles, CA, United States, pp. 210-217, (Springer) [Turki 2013c]
E. Zianbetov, D. Galayko, F. Anceau, M. Javidan, Ch. Shan, O. Billoint, A. Korniienko, E. Colinet, G. Scorletti, J.‑M. Akre, J. Juillard : “Distributed clock generator for synchronous SoC using ADPLL network”, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San José, CA, United States, pp. 1-4, (IEEE) [Zianbetov 2013]