CIAN - Conference papers

Current teams :	ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL
Former team :	ACASA

Publications CIAN	2023	2024	Total
Books	0	0	0
Edited books	0	0	0
Journal articles	7	1	8
Book chapters	1	0	1
Conference papers	6	2	8
Habilitations	0	0	0
Thesis	2	1	3

LIP6

M. Abdoallah, M. Dessouky, M.‑M. Louërat, H. Gicquel, A. Shousha : “Pipelined ADC Design Exploration Methodology Employing Circuit-System Refinement”, Electronics, Communications and Photonics Conference, Riyadh, Saudi Arabia, pp. 1-4, (IEEE) [Abdoallah 2011]
H. Adel, M.‑M. Louërat, H. Gicquel, M. Sabut : “Low Voltage Techniques for Pipelined A/D Converters”, Colloque GDR SOC SIP, Lyon, France, pp. 1-2 [Adel 2011]
J.‑M. Akre, J. Juillard, M. Javidan, E. Zianbetov, D. Galayko, A. Korniienko, E. Colinet : “A Design Approach for Networks of Self-Sampled All-Digital Phase-Locked Loops”, 20^th European Conference on Circuit theory and Design (ECCTD'11), Linköping, Sweden, pp. 725-728 [Akre 2011]
E. Amouri, Z. Marrakchi, H. Mehrez : “Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA”, 6^th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2011, Montpellier, France, pp. 1-4, (IEEE) [Amouri 2011]
Ah. Ashry, H. Aboushady : “A 3.6GS/s, 15mW, 50dB SNDR, 28MHz bandwidth RF ΣΔ ADC with a FoM of 1pJ/bit in 130nm CMOS”, CICC 2011 - Custom Integrated Circuits Conference, San Jose, CA, United States, pp. 1-4, (IEEE) [Ashry 2011a]
Ah. Ashry, H. Aboushady : “A 4th Order Subsampled RF ΣΔ ADC Centered at 2.4GHz with a Sine-Shaped Feedback DAC”, European Solid-State Circuits Conference (ESSCIRC'11), Helsinki, Finland, pp. 263-266, (IEEE) [Ashry 2011b]
Ah. Ashry, H. Aboushady : “Sine-Shaping Mixer for Continuous-Time ΣΔ ADCs”, IEEE International Symposium on Circuits and Systems (ISCAS'11), Rio de Janeiro, Brazil, pp. 1113-1116, (IEEE) [Ashry 2011c]
S. Belloeil, R. Chotin‑Avot, H. Mehrez : “Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools”, ISQED 2011 - 12^th International Symposium on Quality Electronic Design, Santa Clara, CA, United States, pp. 502-507, (IEEE) [Belloeil 2011]
U. Farooq, H. Parvez, E. Amouri, H. Mehrez, Z. Marrakchi : “Exploring the Effect of LUT and Arity Size on a Tree-based Application Specific Inflexible FPGA”, International conference on Design & Technology of Integrated Systems (DTIS), Athens, Greece, pp. 1-6, (IEEE) [Farooq 2011a]
U. Farooq, H. Parvez, Z. Marrakchi, H. Mehrez : “Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA”, The 7^th International Symposium on Applied Reconfigurable Computing, vol. 6578, Lecture Notes in Computer Science, Belfast, United Kingdom, pp. 218-229, (Springer) [Farooq 2011c]
Hélder R. Florentino, Raimundo C. S. Freire, Alan V. S. Sá, C. Florentino, D. Galayko : “Electrostatic vibration energy harvester with piezoelectric start-up generator”, Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, Rio de Janeiro, Brazil, pp. 1343-1346, (IEEE) [Florentino 2011b]
D. Galayko, R. Guillemet, A. Dudka, Ph. Basset : “Comprehensive dynamic and stability analysis of electrostatic Vibration Energy Harvester (E-VEH)”, Solid-State Sensors, Actuators and Microsystems Conference (TRANSDUCERS), 2011 16^th International, Beijing, China, pp. 2382-2385, (IEEE) [Galayko 2011b]
F. Hamzaoui, R. Chotin‑Avot, M. Machhout, H. Mehrez, H. Belmabrouk : “Quantum circuits design and simulation”, The First International Conference on "Research to Applications & Markets" (RAM 2011), Monastir, Tunisia, pp. 115-115 [Hamzaoui 2011]
R. Iskander, M.‑M. Louërat : “Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties”, IEEE MOS-AK/GSA Workshop, Paris, France, pp. 1-2 [Iskander 2011]
F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “Analog Circuits Sizing Using Bipartite Graphs”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea, Republic of, pp. 1-4 [Javid 2011a]
M. Javidan, E. Zianbetov, F. Anceau, D. Galayko, A. Korniienko, E. Colinet, G. Scorletti, J.‑M. Akre, J. Juillard : “All-digital PLL array provides reliable distributed clock for SOCs”, Proceedings of the 2011 IEEE International Symposium of Circuits and Systems, Rio de Janeiro, Brazil, pp. 2589-2592, (IEEE) [Javidan 2011a]
M. Javidan, E. Zianbetov, F. Anceau, D. Galayko, E. Colinet, J. Juillard : “A novel technique to reduce the metastability of Bang-Bang Phase Frequency Detectors”, International Symposium on Circuits and Systems (ISCAS'11), Rio de Janeiro, Brazil, pp. 2577-2580 [Javidan 2011b]
A. Korniienko, G. Scorletti, E. Colinet, E. Blanco, J. Juillard, D. Galayko : “Control law synthesis for distributed multi-agent systems: Application to active clock distribution networks”, Proceedings of the 2011 American Control Conference, San Francisco, CA, United States, pp. 4691-4696 [Korniienko 2011]
B. Robisson, M. Agoyan, S. Bouquet, M. Nguyen, S. Le Henaff, P. Soquet, G. Phan, F. Wajsbürt, P. Bazargan‑Sabet, N. Drach : “Management of the security in smart secure devices”, SSI 2010 - Smart Systems Integration, Dresden, Germany, pp. 1-9 [Robisson 2011a]
B. Robisson, M. Agoyan, S. Le Henaff, P. Soquet, G. Phan, F. Wajsbürt, P. Bazargan‑Sabet : “Implementation of complex strategies of security in secure embedded systems”, NTMS 2011 - 4^th IFIP International Conference on New Technologies, Mobility and Security, Paris, France, pp. 1-5, (IEEE) [Robisson 2011b]
S. Scotti, M. Barnasconi, M.‑M. Louërat, E. Vaumorin : “Design Refinement of Embedded Analogue and Mixed Signal System”, CATRENE DTC conference and EdaForum, Dresden, Germany, pp. 1 [Scotti 2011]
Ch. Shan, E. Zianbetov, M. Javidan, F. Anceau, M. Terosiet, S. Feruglio, D. Galayko, O. Romain, E. Colinet, J. Juillard : “FPGA implementation of reconfigurable ADPLL network for distributed clock generation”, FTP 2011 - International Conference on Field Programmable Technology, New Delhi, India, pp. 1-4, (IEEE) [Shan 2011]
M. Terosiet, S. Feruglio, D. Galayko, P. Garda : “An analytical model of the oscillation period for tri-state inverter based DCO”, Microelectronics (ICM), 2011 International Conference on, Hammamet, Tunisia [Terosiet 2011a]
S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Stack-Based Routing Methodology For Nanometric Analogue CMOS Devices”, The IEEE Virtual Worldwide Forum For PhD Researchers in Electronic Design Automation, (VW FEDA), Southampton, United Kingdom, pp. 1-6 [Youssef 2011a]
S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “Routing Methodology For Nanometric Analog CMOS Devices”, Colloque GDR SOC SIP, Lyon, France, pp. 1-2 [Youssef 2011c]
S. Youssef, F. Javid, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Python-Based Layout-Aware Analog Design Methodology For Nanometric Technologies”, IEEE 6^th International Design and Test Workshop (IDT), Beyrouth, Lebanon, pp. 62-67 [Youssef 2011d]
S. Youssef, F. Javid, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Seamless Representation for Coupling Transistor Sizing with Nanometric CMOS Layout Generation”, 20^th European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, pp. 341-344 [Youssef 2011e]
E. Zianbetov, F. Anceau, M. Javidan, D. Galayko, E. Colinet, J. Juillard : “A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation”, ISCAS 2011 - IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, pp. 2845-2848, (IEEE) [Zianbetov 2011a]
E. Zianbetov, M. Javidan, F. Anceau, D. Galayko, E. Colinet, J. Juillard : “A 2GHz CMOS DCO with optimized architecture for high speed clocking”, Proceedings of International Symposium on Circuits and Systems (ISCAS'11), Rio de Janeiro, Brazil, pp. 2845-2848 [Zianbetov 2011b]